remove trailing whitespace

[coreboot.git] / src / southbridge / amd / sb700 / early_setup.c

diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 7345cdeca3841fa824739aecd0f2ea2593f06436..1f46da2228828f9b8f27d944694d9543d5b95dcc 100644 (file)
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -20,14 +20,19 @@
 #ifndef _SB700_EARLY_SETUP_C_
 #define _SB700_EARLY_SETUP_C_
 
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+
 #include <reset.h>
 #include <arch/cpu.h>
 #include <cbmem.h>
 #include "sb700.h"
-#include "smbus.c"
+#include "smbus.h"
 
-#define SMBUS_IO_BASE 0x6000   /* Is it a temporary SMBus I/O base address? */
-        /*SIZE 0x40 */
 
 static void pmio_write(u8 reg, u8 value)
 {
@@ -129,7 +134,7 @@ static u8 set_sb700_revision(void)
 *      Console output through any port besides 0x3f8 is unsupported.
 *      If you use FWH ROMs, you have to setup IDSEL.
 ***************************************/
-static void sb7xx_51xx_lpc_init(void)
+void sb7xx_51xx_lpc_init(void)
 {
        u8 reg8;
        u32 reg32;
@@ -149,7 +154,7 @@ static void sb7xx_51xx_lpc_init(void)
        reg32 |= 1 << 20;
        pci_write_config32(dev, 0x64, reg32);
 
-#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100
+#if CONFIG_SOUTHBRIDGE_AMD_SP5100
        post_code(0x66);
        dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0);     /* LPC Controller */
        reg8 = pci_read_config8(dev, 0xBB);
@@ -163,7 +168,7 @@ static void sb7xx_51xx_lpc_init(void)
        // XXX Serial port decode on LPC is hardcoded to 0x3f8
        reg8 = pci_read_config8(dev, 0x44);
        reg8 |= 1 << 6;
-#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100
+#if CONFIG_SOUTHBRIDGE_AMD_SP5100
 #if CONFIG_TTYS0_BASE == 0x2f8
        reg8 |= 1 << 7;
 #endif
@@ -216,7 +221,7 @@ void sb7xx_51xx_disable_wideio(u8 wio_index)
 }
 
 /* what is its usage? */
-static u32 get_sbdn(u32 bus)
+u32 __attribute__ ((weak)) get_sbdn(u32 bus)
 {
        device_t dev;
 
@@ -233,7 +238,7 @@ static u8 dual_core(void)
 /*
  * RPR 2.4 C-state and VID/FID change for the K8 platform.
  */
-static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
+void __attribute__((weak)) enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
 {
        u8 byte;
        byte = pmio_read(0x9a);
@@ -284,22 +289,6 @@ static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
        pmio_write(0x67, 0x6);
 }
 
-void hard_reset(void)
-{
-       set_bios_reset();
-
-       /* full reset */
-       outb(0x0a, 0x0cf9);
-       outb(0x0e, 0x0cf9);
-}
-
-void soft_reset(void)
-{
-       set_bios_reset();
-       /* link reset */
-       outb(0x06, 0x0cf9);
-}
-
 void sb7xx_51xx_pci_port80(void)
 {
        u8 byte;
@@ -369,7 +358,7 @@ static void sb700_devices_por_init(void)
 {
        device_t dev;
        u8 byte;
-#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100
+#if CONFIG_SOUTHBRIDGE_AMD_SP5100
        u32 dword;
 #endif
 
@@ -505,7 +494,7 @@ static void sb700_devices_por_init(void)
        /* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */
        pci_write_config8(dev, 0x50, 0x01);
 
-#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100
+#if CONFIG_SOUTHBRIDGE_AMD_SP5100
        /* SP5100 default SATA mode is RAID5 MODE */
        dev = pci_locate_device(PCI_ID(0x1002, 0x4393), 0);
        /* Set SATA Operation Mode, Set to IDE mode */
@@ -681,7 +670,7 @@ static void sb700_por_init(void)
 /*
 * It should be called during early POST after memory detection and BIOS shadowing but before PCI bus enumeration.
 */
-static void sb7xx_51xx_before_pci_init(void)
+void sb7xx_51xx_before_pci_init(void)
 {
        sb700_pci_cfg();
 }
@@ -689,18 +678,13 @@ static void sb7xx_51xx_before_pci_init(void)
 /*
 * This function should be called after enable_sb700_smbus().
 */
-static void sb7xx_51xx_early_setup(void)
+void sb7xx_51xx_early_setup(void)
 {
        printk(BIOS_INFO, "sb700_early_setup()\n");
        sb700_por_init();
        sb700_acpi_init();
 }
 
-static int smbus_read_byte(u32 device, u32 address)
-{
-       return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
-
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
 {
        int i;
@@ -732,7 +716,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
 }
 
 #if CONFIG_HAVE_ACPI_RESUME == 1
-static int acpi_is_wakeup_early(void)
+int acpi_is_wakeup_early(void)
 {
        u16 tmp;
        tmp = inw(ACPI_PM1_CNT_BLK);