pci stuff: too much hax now, trying rd890 patch (not merged yet)

[coreboot.git] / src / southbridge / amd / rs780 / rs780.c

diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c
index d8f1be3dbe74fc17a5472b0814df31624f1e9b1e..2c6a0339eb4b43134d7e08258afe3e5519a42749 100644 (file)
--- a/src/southbridge/amd/rs780/rs780.c
+++ b/src/southbridge/amd/rs780/rs780.c
@@ -186,11 +186,12 @@ static void rs780_nb_pci_table(device_t nb_dev)
 #endif
 }
 
+#if 0
 static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
 {
        /* NB_InitGFXStraps */
        u32 MMIOBase, apc04, apc18, apc24, romstrap2;
-       msr_t pcie_mmio_save;
+       msr_t pcie_mmio_save = { 0, 0 };
        volatile u32 * strap;
 
        // disable processor pcie mmio, if enabled
@@ -223,7 +224,7 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
 #if (CONFIG_GFXUMA == 1)
        extern uint64_t uma_memory_size;
        // bits 7-9: aperture size
-       // 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g 
+       // 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g
        if (uma_memory_size == 0x02000000) romstrap2 |= 3 << 7;
        if (uma_memory_size == 0x04000000) romstrap2 |= 2 << 7;
        if (uma_memory_size == 0x08000000) romstrap2 |= 0 << 7;
@@ -272,6 +273,7 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
 
        printk(BIOS_INFO, "GC is accessible from now on.\n");
 }
+#endif
 
 /***********************************************
 *      0:00.0  NBCFG   :
@@ -292,6 +294,7 @@ void rs780_enable(device_t dev)
        device_t nb_dev = 0, sb_dev = 0;
        int dev_ind;
 
+       printk(BIOS_INFO, "%s: WHAT THE FUCK\n", __func__);
        printk(BIOS_INFO, "rs780_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev));
 
        nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
@@ -325,15 +328,19 @@ void rs780_enable(device_t dev)
 
        case 1: /* bus0, dev1, APC. */
                printk(BIOS_INFO, "Bus-0, Dev-1, Fun-0.\n");
+#if 0
                rs780_nb_gfx_dev_table(nb_dev, dev);
+#endif
                break;
        case 2:         /* bus0, dev2,3, two GFX */
        case 3:
                printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled);
                set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
                                       (dev->enabled ? 0 : 1) << dev_ind);
+#if 0
                if (dev->enabled)
                        rs780_gfx_init(nb_dev, dev, dev_ind);
+#endif
                break;
        case 4:         /* bus0, dev4-7, four GPPSB */
        case 5:
@@ -362,11 +369,15 @@ void rs780_enable(device_t dev)
                if (dev->enabled)
                        rs780_gpp_sb_init(nb_dev, dev, dev_ind);
 
-               if (dev_ind == 10) disable_pcie_bar3(nb_dev);
+               if (dev_ind == 10) {
+                       disable_pcie_bar3(nb_dev);
+                       pcie_hide_unused_ports(nb_dev);
+               }
                break;
        default:
                printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev));
        }
+       printk(BIOS_INFO, "rs780_enable: done\n");
 }
 
 struct chip_operations southbridge_amd_rs780_ops = {