-/*\r
- *****************************************************************************\r
- *\r
- * This file is part of the coreboot project.\r
- *\r
- * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
- *\r
- * This program is free software; you can redistribute it and/or modify\r
- * it under the terms of the GNU General Public License as published by\r
- * the Free Software Foundation; version 2 of the License.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- * You should have received a copy of the GNU General Public License\r
- * along with this program; if not, write to the Free Software\r
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
- * ***************************************************************************\r
- *\r
- */\r
-\r
-#ifndef _AMD_SBPLATFORM_H_\r
-#define _AMD_SBPLATFORM_H_\r
-\r
-#include <southbridge/amd/cimx_wrapper/sb800/cbtypes.h>\r
-typedef UINT64 PLACEHOLDER;\r
-#include <southbridge/amd/cimx_wrapper/sb800/Amdlib.h>\r
-#include <southbridge/amd/cimx_wrapper/sb800/Amd.h>\r
-#include <vendorcode/amd/cimx/lib/amdlib32.h> //TODO merge with agesa wrapper\r
-#include <vendorcode/amd/cimx/sb800/SB800.h>\r
-#include <vendorcode/amd/cimx/sb800/SBTYPE.h>\r
-#include <vendorcode/amd/cimx/sb800/ACPILIB.h>\r
-#include <vendorcode/amd/cimx/sb800/SBDEF.h>\r
-#include <vendorcode/amd/cimx/sb800/AMDSBLIB.h>\r
-#include <vendorcode/amd/cimx/sb800/SBSUBFUN.h>\r
-#include <vendorcode/amd/cimx/sb800/OEM.h>\r
-\r
-#ifdef NULL\r
- #undef NULL\r
-#endif\r
-#define NULL 0\r
-\r
-#ifndef SBOEM_ACPI_RESTORE_SWSMI\r
- #define SBOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3\r
- #define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4\r
-#endif\r
-\r
-#ifndef _AMD_NB_CIM_X_PROTOCOL_H_\r
-\r
-/// Extended PCI Address\r
-typedef struct _EXT_PCI_ADDR {\r
- UINT32 Reg :16; ///< / PCI Register\r
- UINT32 Func:3; ///< / PCI Function\r
- UINT32 Dev :5; ///< / PCI Device\r
- UINT32 Bus :8; ///< / PCI Address\r
-} EXT_PCI_ADDR;\r
-\r
-/// PCI Address\r
-typedef union _PCI_ADDR {\r
- UINT32 ADDR; ///< / 32 bit Address\r
- EXT_PCI_ADDR Addr; ///< / Extended PCI Address\r
-} PCI_ADDR;\r
-#endif\r
-\r
-#define FIXUP_PTR(ptr) ptr\r
-\r
-//------------------------------------------------------------------------------------------------------------------------//\r
-/**\r
- * SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over\r
- * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable\r
- * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal\r
- * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable\r
- * HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)\r
- * IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00)\r
- * SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable\r
- * SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL)\r
- * NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable\r
- * AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable\r
- * ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable\r
- * GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable\r
- * GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable\r
- * GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable\r
- * GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable\r
- * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable\r
- * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable\r
- * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable\r
- * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Nerver Power down (0x11)\r
- * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00)\r
- * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz\r
- * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable\r
- * SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable\r
- * SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)\r
- * SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)\r
- * SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable\r
- * SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable\r
- * SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable\r
- * SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable\r
- * AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable\r
- * TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable\r
- * ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable\r
- * OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable\r
- * EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable\r
- * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable\r
- * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable\r
- */\r
-#define SB_CIMx_PARAMETER 0x02\r
-\r
-// Generic \r
-#define cimSpreadSpectrumDefault TRUE\r
-#define cimSpreadSpectrumTypeDefault 0x00 // Normal\r
-#define cimHpetTimerDefault TRUE\r
-#define cimHpetMsiDisDefault FALSE // Enable\r
-#define cimIrConfigDefault 0x00 // Disable\r
-#define cimSpiFastReadEnableDefault 0x00 // Disable\r
-#define cimSpiFastReadSpeedDefault 0x00 // NULL\r
-// GPP/AB Controller \r
-#define cimNbSbGen2Default TRUE\r
-#define cimAlinkPhyPllPowerDownDefault TRUE\r
-#define cimResetCpuOnSyncFloodDefault TRUE\r
-#define cimGppGen2Default FALSE\r
-#define cimGppMemWrImproveDefault TRUE\r
-#define cimGppPortAspmDefault FALSE\r
-#define cimGppLaneReversalDefault FALSE\r
-#define cimGppPhyPllPowerDownDefault TRUE \r
-// USB Controller\r
-#define cimUsbPhyPowerDownDefault FALSE\r
-// GEC Controller\r
-#define cimSBGecDebugBusDefault FALSE\r
-#define cimSBGecPwrDefault 0x03\r
-// Sata Controller \r
-#define cimSataSetMaxGen2Default 0x00\r
-#define cimSATARefClkSelDefault 0x10\r
-#define cimSATARefDivSelDefault 0x80\r
-#define cimSataAggrLinkPmCapDefault TRUE\r
-#define cimSataPortMultCapDefault TRUE\r
-#define cimSataPscCapDefault 0x00 // Enable\r
-#define cimSataSscCapDefault 0x00 // Enable\r
-#define cimSataFisBasedSwitchingDefault FALSE \r
-#define cimSataCccSupportDefault FALSE\r
-#define cimSataClkAutoOffDefault FALSE\r
-#define cimNativepciesupportDefault FALSE\r
-// Fusion Related \r
-#define cimAcDcMsgDefault FALSE\r
-#define cimTimerTickTrackDefault FALSE\r
-#define cimClockInterruptTagDefault FALSE\r
-#define cimOhciTrafficHandingDefault FALSE\r
-#define cimEhciTrafficHandingDefault FALSE\r
-#define cimFusionMsgCMultiCoreDefault FALSE\r
-#define cimFusionMsgCStageDefault FALSE\r
-\r
-#endif // _AMD_SBPLATFORM_H_\r
+/*
+ *****************************************************************************
+ *
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _AMD_SBPLATFORM_H_
+#define _AMD_SBPLATFORM_H_
+
+#include <southbridge/amd/cimx_wrapper/sb800/cbtypes.h>
+typedef UINT64 PLACEHOLDER;
+#include <southbridge/amd/cimx_wrapper/sb800/Amdlib.h>
+#include <southbridge/amd/cimx_wrapper/sb800/Amd.h>
+#include <vendorcode/amd/cimx/lib/amdlib32.h> //TODO merge with agesa wrapper
+#include <vendorcode/amd/cimx/sb800/SB800.h>
+#include <vendorcode/amd/cimx/sb800/SBTYPE.h>
+#include <vendorcode/amd/cimx/sb800/ACPILIB.h>
+#include <vendorcode/amd/cimx/sb800/SBDEF.h>
+#include <vendorcode/amd/cimx/sb800/AMDSBLIB.h>
+#include <vendorcode/amd/cimx/sb800/SBSUBFUN.h>
+#include <vendorcode/amd/cimx/sb800/OEM.h>
+
+#ifdef NULL
+ #undef NULL
+#endif
+#define NULL 0
+
+#ifndef SBOEM_ACPI_RESTORE_SWSMI
+ #define SBOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3
+ #define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4
+#endif
+
+#ifndef _AMD_NB_CIM_X_PROTOCOL_H_
+
+/// Extended PCI Address
+typedef struct _EXT_PCI_ADDR {
+ UINT32 Reg :16; ///< / PCI Register
+ UINT32 Func:3; ///< / PCI Function
+ UINT32 Dev :5; ///< / PCI Device
+ UINT32 Bus :8; ///< / PCI Address
+} EXT_PCI_ADDR;
+
+/// PCI Address
+typedef union _PCI_ADDR {
+ UINT32 ADDR; ///< / 32 bit Address
+ EXT_PCI_ADDR Addr; ///< / Extended PCI Address
+} PCI_ADDR;
+#endif
+
+#define FIXUP_PTR(ptr) ptr
+
+//------------------------------------------------------------------------------------------------------------------------//
+/**
+ * SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over
+ * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable
+ * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal
+ * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable
+ * HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
+ * IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00)
+ * SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable
+ * SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL)
+ * NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable
+ * AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
+ * ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable
+ * GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable
+ * GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable
+ * GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable
+ * GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable
+ * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
+ * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable
+ * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable
+ * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Nerver Power down (0x11)
+ * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00)
+ * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz
+ * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable
+ * SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable
+ * SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
+ * SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
+ * SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable
+ * SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable
+ * SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable
+ * SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable
+ * AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable
+ * TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable
+ * ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable
+ * OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
+ * EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
+ * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable
+ * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable
+ */
+#define SB_CIMx_PARAMETER 0x02
+
+// Generic
+#define cimSpreadSpectrumDefault TRUE
+#define cimSpreadSpectrumTypeDefault 0x00 // Normal
+#define cimHpetTimerDefault TRUE
+#define cimHpetMsiDisDefault FALSE // Enable
+#define cimIrConfigDefault 0x00 // Disable
+#define cimSpiFastReadEnableDefault 0x00 // Disable
+#define cimSpiFastReadSpeedDefault 0x00 // NULL
+// GPP/AB Controller
+#define cimNbSbGen2Default TRUE
+#define cimAlinkPhyPllPowerDownDefault TRUE
+#define cimResetCpuOnSyncFloodDefault TRUE
+#define cimGppGen2Default FALSE
+#define cimGppMemWrImproveDefault TRUE
+#define cimGppPortAspmDefault FALSE
+#define cimGppLaneReversalDefault FALSE
+#define cimGppPhyPllPowerDownDefault TRUE
+// USB Controller
+#define cimUsbPhyPowerDownDefault FALSE
+// GEC Controller
+#define cimSBGecDebugBusDefault FALSE
+#define cimSBGecPwrDefault 0x03
+// Sata Controller
+#define cimSataSetMaxGen2Default 0x00
+#define cimSATARefClkSelDefault 0x10
+#define cimSATARefDivSelDefault 0x80
+#define cimSataAggrLinkPmCapDefault TRUE
+#define cimSataPortMultCapDefault TRUE
+#define cimSataPscCapDefault 0x00 // Enable
+#define cimSataSscCapDefault 0x00 // Enable
+#define cimSataFisBasedSwitchingDefault FALSE
+#define cimSataCccSupportDefault FALSE
+#define cimSataClkAutoOffDefault FALSE
+#define cimNativepciesupportDefault FALSE
+// Fusion Related
+#define cimAcDcMsgDefault FALSE
+#define cimTimerTickTrackDefault FALSE
+#define cimClockInterruptTagDefault FALSE
+#define cimOhciTrafficHandingDefault FALSE
+#define cimEhciTrafficHandingDefault FALSE
+#define cimFusionMsgCMultiCoreDefault FALSE
+#define cimFusionMsgCStageDefault FALSE
+
+#endif // _AMD_SBPLATFORM_H_
projects / coreboot.git / blobdiff