remove trailing whitespace

[coreboot.git] / src / southbridge / amd / cimx / sb800 / bootblock.c

diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
index aaec03cbea4507095f54387c78dca5feac36673c..0a339b02f740b52e143c145e8739a677a46ee78e 100644 (file)
--- a/src/southbridge/amd/cimx/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx/sb800/bootblock.c
@@ -39,8 +39,8 @@ static void enable_rom(void)
        pci_io_write_config32(dev, 0x44, dword);
 
        /* SB800 LPC Bridge 0:20:3:48h.
-        * BIT0: Port Enable for SuperIO 0x2E-0x2F 
-        * BIT1: Port Enable for SuperIO 0x4E-0x4F 
+        * BIT0: Port Enable for SuperIO 0x2E-0x2F
+        * BIT1: Port Enable for SuperIO 0x4E-0x4F
         * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
         * BIT6: Port Enable for RTC IO 0x70-0x73
         * BIT21: Port Enable for Port 0x80
@@ -49,10 +49,9 @@ static void enable_rom(void)
        dword |= (1 << 0) | (1 << 1) | (1 << 4) | (1 << 6) | (1 << 21);
        pci_io_write_config32(dev, 0x48, dword);
 
-       /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */
-       /* Set the 4MB enable bits */
+       /* Enable rom access */
        word = pci_io_read_config16(dev, 0x6c);
-       word = 0xFFC0;
+       word = 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6);
        pci_io_write_config16(dev, 0x6c, word);
 }
 
@@ -85,10 +84,31 @@ static void enable_spi_fast_mode(void)
        pci_io_write_config32(dev, 0xa0, save);
 }
 
+static void enable_clocks(void)
+{
+       u8 reg8;
+       u32 reg32;
+       volatile u32 *acpi_mmio = (void *) (0xFED80000 + 0xE00 + 0x40);
+
+       // Program AcpiMmioEn to enable MMIO access to MiscCntrl register
+       outb(0x24, 0xCD6);
+       reg8 = inb(0xCD7);
+       reg8 |= 1;
+       reg8 &= ~(1 << 1);
+       outb(reg8, 0xCD7);
+
+       // Program SB800 MiscCntrl Device_CLK1_sel for 48 MHz (default is 14 MHz)
+       reg32 = *acpi_mmio;
+       reg32 &= ~((1 << 0) | (1 << 2));
+       reg32 |= 1 << 1;
+       *acpi_mmio = reg32;
+}
+
 static void bootblock_southbridge_init(void)
 {
        /* Setup the rom access for 2M */
        enable_rom();
        enable_prefetch();
        enable_spi_fast_mode();
+       enable_clocks();
 }