Add support for Intel Sandybridge CPU (northbridge part)

[coreboot.git] / src / northbridge / intel / sandybridge / acpi / sandybridge.asl

diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
new file mode 100644 (file)
index 0000000..64b5d8f
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "hostbridge.asl"
+#include "../sandybridge.h"
+
+/* PCI Device Resource Consumption */
+Device (PDRC)
+{
+       Name (_HID, EISAID("PNP0C02"))
+       Name (_UID, 1)
+
+       Name (PDRS, ResourceTemplate() {
+               Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA
+               Memory32Fixed(ReadWrite, DEFAULT_MCHBAR,   0x00004000)
+               Memory32Fixed(ReadWrite, DEFAULT_DMIBAR,   0x00001000)
+               Memory32Fixed(ReadWrite, DEFAULT_EPBAR,    0x00001000)
+               Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
+               Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
+               Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
+               Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
+
+#if CONFIG_CHROMEOS_RAMOOPS
+               Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
+                                        CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
+#endif
+
+               /* Required for SandyBridge sighting 3715511 */
+               Memory32Fixed(ReadWrite, 0x20000000, 0x00200000)
+               Memory32Fixed(ReadWrite, 0x40000000, 0x00200000)
+       })
+
+       // Current Resource Settings
+       Method (_CRS, 0, Serialized)
+       {
+               Return(PDRS)
+       }
+}
+
+// Integrated graphics 0:2.0
+#include "igd.asl"