* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <console/console.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <pc80/mc146818rtc.h>
#include <spd.h>
+#include <string.h>
+#include <arch/romcc_io.h>
#include "raminit.h"
#include "i945.h"
+#include <cbmem.h>
+
+struct cbmem_entry *get_cbmem_toc(void)
+{
+ return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
+}
/* Debugging macros. */
#if CONFIG_DEBUG_RAM_SETUP
#define RAM_EMRS_2 (0x1 << 21)
#define RAM_EMRS_3 (0x2 << 21)
+static int get_dimm_spd_address(struct sys_info *sysinfo, int device)
+{
+ if (sysinfo->spd_addresses)
+ return sysinfo->spd_addresses[device];
+ else
+ return DIMM0 + device;
+
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device, address);
+}
+
static __attribute__((noinline)) void do_ram_command(u32 command)
{
u32 reg32;
MCHBAR32(DCC) = reg32; /* This is the actual magic */
PRINTK_DEBUG("...done\n");
+
+ udelay(1);
}
static void ram_read32(u32 offset)
}
#if CONFIG_DEBUG_RAM_SETUP
-static void sdram_dump_mchbar_registers(void)
+void sdram_dump_mchbar_registers(void)
{
int i;
printk(BIOS_DEBUG, "Dumping MCHBAR Registers\n");
static int memclk(void)
{
int offset = 0;
-#ifdef CHIPSET_I945GM
+#if CONFIG_NORTHBRIDGE_INTEL_I945GM
offset++;
#endif
switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) {
return -1;
}
-#ifdef CHIPSET_I945GM
-static int fsbclk(void)
+#if CONFIG_NORTHBRIDGE_INTEL_I945GM
+static u16 fsbclk(void)
{
switch (MCHBAR32(CLKCFG) & 7) {
case 0: return 400;
case 3: return 667;
default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
}
- return -1;
+ return 0xffff;
}
-#endif
-#ifdef CHIPSET_I945GC
-static int fsbclk(void)
+#elif CONFIG_NORTHBRIDGE_INTEL_I945GC
+static u16 fsbclk(void)
{
switch (MCHBAR32(CLKCFG) & 7) {
case 0: return 1066;
case 2: return 800;
default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
}
- return -1;
+ return 0xffff;
}
#endif
{
u32 reg32;
-#ifdef MAXIMUM_SUPPORTED_FREQUENCY
- return MAXIMUM_SUPPORTED_FREQUENCY;
+#if CONFIG_MAXIMUM_SUPPORTED_FREQUENCY
+ return CONFIG_MAXIMUM_SUPPORTED_FREQUENCY;
#endif
reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */
reg8 |= (1<<7);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
- /* clear self refresh if not wake-up from suspend */
- if (sysinfo->boot_path != 2) {
+ /* clear self refresh status if check is disabled or not a resume */
+ if (!CONFIG_CHECK_SLFRCS_ON_RESUME || sysinfo->boot_path != 2) {
MCHBAR8(0xf14) |= 3;
} else {
/* Validate self refresh config */
/**
* i945 supports two DIMMs, in two configurations:
*
- * - single channel with two dimms
- * - dual channel with one dimm per channel
+ * - single channel with two DIMMs
+ * - dual channel with one DIMM per channel
*
- * In practice dual channel mainboards have their spd at 0x50, 0x52
- * whereas single channel configurations have their spd at 0x50/x51
+ * In practice dual channel mainboards have their SPD at 0x50/0x52
+ * whereas single channel configurations have their SPD at 0x50/0x51.
*
* The capability register knows a lot about the channel configuration
- * but for now we stick with the information we gather from the SPD
- * ROMs
+ * but for now we stick with the information we gather via SPD.
*/
if (sdram_capabilities_dual_channel()) {
*/
for (i=0; i<(2 * DIMM_SOCKETS); i++) {
- u8 reg8, device = DIMM_SPD_BASE + i;
+ int device = get_dimm_spd_address(sysinfo, i);
+ u8 reg8;
/* Initialize the socket information with a sane value */
sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED;
continue;
/* Is the current DIMM a stacked DIMM? */
- if (spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_DIMM_BANKS) & (1 << 4))
+ if (spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_NUM_DIMM_BANKS) & (1 << 4))
sysinfo->package = 1;
}
}
for (i=0; i<2*DIMM_SOCKETS; i++) {
if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED)
- cas_mask &= spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
+ cas_mask &= spd_read_byte(get_dimm_spd_address(sysinfo, i),
+ SPD_ACCEPTABLE_CAS_LATENCIES);
}
if(!cas_mask) {
PRINTK_DEBUG("Probing Speed %d\n", j);
for (i=0; i<2*DIMM_SOCKETS; i++) {
+ int device = get_dimm_spd_address(sysinfo, i);
int current_cas_mask;
PRINTK_DEBUG(" DIMM: %d\n", i);
continue;
}
- current_cas_mask = spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
+ current_cas_mask = spd_read_byte(device, SPD_ACCEPTABLE_CAS_LATENCIES);
while (current_cas_mask) {
int highest_supported_cas = 0, current_cas = 0;
highest_supported_cas = 4;
} else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
highest_supported_cas = 3;
+ } else {
+ die("Invalid max. CAS.\n");
}
if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
current_cas = 3;
current_cas = 4;
} else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
current_cas = 5;
+ } else {
+ die("Invalid CAS.\n");
}
idx = highest_supported_cas - current_cas;
PRINTK_DEBUG("idx=%d, ", idx);
- PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]));
- PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]));
+ PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(device, spd_lookup_table[2*idx]));
+ PRINTK_DEBUG("tAC=%x", spd_read_byte(device, spd_lookup_table[(2*idx)+1]));
- if (spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
- spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
+ if (spd_read_byte(device, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
+ spd_read_byte(device, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
PRINTK_DEBUG(": OK\n");
break;
}
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
- reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
+ reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
if (!reg8) {
die("Invalid tRAS value.\n");
}
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
- reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ROW_PRECHARGE_TIME);
+ reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_ROW_PRECHARGE_TIME);
if (!reg8) {
die("Invalid tRP value.\n");
}
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
- reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_RAS_TO_CAS_DELAY);
+ reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_RAS_TO_CAS_DELAY);
if (!reg8) {
die("Invalid tRCD value.\n");
}
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
- reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_WRITE_RECOVERY_TIME);
+ reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_WRITE_RECOVERY_TIME);
if (!reg8) {
die("Invalid tWR value.\n");
}
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
- refresh = spd_read_byte(DIMM_SPD_BASE + i, SPD_REFRESH) & ~(1 << 7);
+ refresh = spd_read_byte(get_dimm_spd_address(sysinfo, i),
+ SPD_REFRESH) & ~(1 << 7);
/* 15.6us */
if (!refresh)
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
- if (!(spd_read_byte(DIMM_SPD_BASE + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
+ if (!(spd_read_byte(get_dimm_spd_address(sysinfo, i),
+ SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n");
}
}
return nc;
}
-#ifdef CHIPSET_I945GM
+#if CONFIG_NORTHBRIDGE_INTEL_I945GM
/* Strength multiplier tables */
static const u8 dual_channel_strength_multiplier[] = {
0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11
};
-#endif
-#ifdef CHIPSET_I945GC
+#elif CONFIG_NORTHBRIDGE_INTEL_I945GC
static const u8 dual_channel_strength_multiplier[] = {
0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
unsigned long side2;
};
-static struct dimm_size sdram_get_dimm_size(u16 device)
+static struct dimm_size sdram_get_dimm_size(struct sys_info *sysinfo, u16 dimmno)
{
/* Calculate the log base 2 size of a DIMM in bits */
struct dimm_size sz;
- int value, low, rows, columns;
+ int value, low, rows, columns, device;
+ device = get_dimm_spd_address(sysinfo, dimmno);
sz.side1 = 0;
sz.side2 = 0;
*/
sz.side1 = 0;
sz.side2 = 0;
- out:
+out:
return sz;
}
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
- sz = sdram_get_dimm_size(DIMM_SPD_BASE + i);
+ sz = sdram_get_dimm_size(sysinfo, i);
- sysinfo->banks[i] = spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_BANKS_PER_SDRAM); /* banks */
+ sysinfo->banks[i] = spd_read_byte(get_dimm_spd_address(sysinfo, i),
+ SPD_NUM_BANKS_PER_SDRAM); /* banks */
if (sz.side1 < 30)
die("DDR-II rank size smaller than 128MB is not supported.\n");
continue;
}
- device = DIMM_SPD_BASE + i;
+ device = get_dimm_spd_address(sysinfo, i);
value = spd_read_byte(device, SPD_NUM_ROWS); /* rows */
columnsrows = (value & 0x0f);
MCHBAR32(PLLMON) = 0x80800000;
sysinfo->fsb_frequency = fsbclk();
- if (sysinfo->fsb_frequency == -1)
+ if (sysinfo->fsb_frequency == 0xffff)
die("Unsupported FSB speed");
/* Program CPCTL according to FSB speed */
/**
* We add the indices according to our clocks from CLKCFG.
*/
-#ifdef CHIPSET_I945GM
+#if CONFIG_NORTHBRIDGE_INTEL_I945GM
static const u32 data_clock_crossing[] = {
0x00100401, 0x00000000, /* DDR400 FSB400 */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistant */
};
-#endif
-#ifdef CHIPSET_I945GC
+#elif CONFIG_NORTHBRIDGE_INTEL_I945GC
/* i945 G/P */
static const u32 data_clock_crossing[] = {
0xffffffff, 0xffffffff, /* nonexistant */
if (sysinfo->interleaved) {
reg32 = MCHBAR32(DCC);
-#if CHANNEL_XOR_RANDOMIZATION
+#if CONFIG_CHANNEL_XOR_RANDOMIZATION
reg32 &= ~(1 << 10);
reg32 |= (1 << 9);
#else
{
u8 clocks[2] = { 0, 0 };
-#ifdef CHIPSET_I945GM
+#if CONFIG_NORTHBRIDGE_INTEL_I945GM
#define CLOCKS_WIDTH 2
-#endif
-#ifdef CHIPSET_I945GC
+#elif CONFIG_NORTHBRIDGE_INTEL_I945GC
#define CLOCKS_WIDTH 3
#endif
if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)
if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
-#ifdef OVERRIDE_CLOCK_DISABLE
+#if CONFIG_OVERRIDE_CLOCK_DISABLE
/* Usually system firmware turns off system memory clock signals
* to unused SO-DIMM slots to reduce EMI and power consumption.
* However, the Kontron 986LCD-M does not like unused clock
* signals to be disabled.
- * If other similar mainboard occur, it would make sense to make
- * this an entry in the sysinfo structure, and pre-initialize that
- * structure in the mainboard's romstage.c main() function.
- * For now an #ifdef will do.
*/
clocks[0] = 0xf; /* force all clock gate pairs to enable */
/**
* @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3
*/
-void sdram_initialize(int boot_path)
+void sdram_initialize(int boot_path, const u8 *spd_addresses)
{
struct sys_info sysinfo;
u8 reg8, cas_mask;
memset(&sysinfo, 0, sizeof(sysinfo));
sysinfo.boot_path = boot_path;
+ sysinfo.spd_addresses = spd_addresses;
/* Look at the type of DIMMs and verify all DIMMs are x8 or x16 width */
sdram_get_dram_configuration(&sysinfo);
unsigned long get_top_of_ram(void)
{
- /* This will not work if TSEG is in place! */
- u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
+ u32 tom;
+ if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & ((1 << 4) | (1 << 3))) {
+ /* IGD enabled, get top of Memory from BSM register */
+ tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
+ } else {
+ tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24;
+ }
+
+ /* if TSEG enabled subtract size */
+ switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM)) {
+ case 0x01:
+ /* 1MB TSEG */
+ tom -= 0x10000;
+ break;
+ case 0x03:
+ /* 2MB TSEG */
+ tom -= 0x20000;
+ break;
+ case 0x05:
+ /* 8MB TSEG */
+ tom -= 0x80000;
+ break;
+ default:
+ /* TSEG either disabled or invalid */
+ break;
+ }
return (unsigned long) tom;
}
projects / coreboot.git / blobdiff