Some more DIMM0 related cleanups and deduplication.

[coreboot.git] / src / northbridge / intel / i855 / raminit.h

diff --git a/src/northbridge/intel/i855/raminit.h b/src/northbridge/intel/i855/raminit.h
index 1f1b34d14b43021a12fcbbab33b7419e51bd7920..2ac0fde62dc8812371dba2c703133723869c440b 100644 (file)
--- a/src/northbridge/intel/i855/raminit.h
+++ b/src/northbridge/intel/i855/raminit.h
@@ -28,9 +28,6 @@
 /* The i855 supports max. 2 dual-sided SO-DIMMs. */
 #define DIMM_SOCKETS 2
 
-/* DIMM0 is at 0x50, DIMM1 is at 0x51. */
-#define DIMM_SPD_BASE   0x50
-
 struct mem_controller {
   device_t d0;
   uint16_t channel0[DIMM_SOCKETS];
@@ -38,5 +35,4 @@ struct mem_controller {
 
 void sdram_initialize(int controllers, const struct mem_controller *ctrl);
 
-
 #endif /* NORTHBRIDGE_INTEL_I855_RAMINIT_H */