Since some people disapprove of white space cleanups mixed in regular commits

[coreboot.git] / src / northbridge / intel / i855 / raminit.c

diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c
index 5d71a27ca17ab392b38b62a904fb5ba5e9843792..386eda10bb18c3520034137cf3baa1ac9d193245 100644 (file)
--- a/src/northbridge/intel/i855/raminit.c
+++ b/src/northbridge/intel/i855/raminit.c
@@ -17,7 +17,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
- 
+
 #include <sdram_mode.h>
 #include <delay.h>
 
@@ -28,7 +28,7 @@
   * Set only what I need until it works, then make it figure things out on boot
   * assumes only one dimm is populated
   */
- 
+
 static void sdram_set_registers(const struct mem_controller *ctrl)
 {
        /*
@@ -40,7 +40,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 static void spd_set_row_attributes(const struct mem_controller *ctrl)
 {
        uint16_t dra_reg;
-       
+
        dra_reg = 0x7733;
        pci_write_config16(ctrl->d0, 0x50, dra_reg);
 }
@@ -48,7 +48,7 @@ static void spd_set_row_attributes(const struct mem_controller *ctrl)
 static void spd_set_dram_controller_mode(const struct mem_controller *ctrl)
 {
        uint32_t drc_reg;
-       
+
        /* drc_reg = 0x00009101; */
        drc_reg = 0x00009901;
        pci_write_config32(ctrl->d0, 0x70, drc_reg);
@@ -57,7 +57,7 @@ static void spd_set_dram_controller_mode(const struct mem_controller *ctrl)
 static void spd_set_dram_timing(const struct mem_controller *ctrl)
 {
        uint32_t drt_reg;
-       
+
        drt_reg = 0x2a004405;
        pci_write_config32(ctrl->d0, 0x60, drt_reg);
 }
@@ -73,7 +73,7 @@ static void spd_set_dram_size(const struct mem_controller *ctrl)
 static void spd_set_dram_pwr_management(const struct mem_controller *ctrl)
 {
        uint32_t pwrmg_reg;
-       
+
        pwrmg_reg = 0x10f10430;
        pci_write_config32(ctrl->d0, 0x68, pwrmg_reg);
 }
@@ -97,31 +97,31 @@ static void spd_set_undocumented_registers(const struct mem_controller *ctrl)
        pci_write_config32(PCI_DEV(0, 0, 0), 0x2c, 0x35808086);
        pci_write_config32(PCI_DEV(0, 0, 0), 0x48, 0xfec10000);
        pci_write_config32(PCI_DEV(0, 0, 0), 0x50, 0x00440100);
-       
+
        pci_write_config32(PCI_DEV(0, 0, 0), 0x58, 0x11111000);
-       
+
        pci_write_config16(PCI_DEV(0, 0, 0), 0x52, 0x0002);
        */
        pci_write_config16(PCI_DEV(0, 0, 0), 0x52, 0x0044);
        /*
        pci_write_config16(PCI_DEV(0, 0, 0), 0x52, 0x0000);
        */
-       pci_write_config32(PCI_DEV(0, 0, 0), 0x58, 0x33333000); 
+       pci_write_config32(PCI_DEV(0, 0, 0), 0x58, 0x33333000);
        pci_write_config32(PCI_DEV(0, 0, 0), 0x5c, 0x33333333);
        /*
        pci_write_config32(PCI_DEV(0, 0, 0), 0x60, 0x0000390a);
        pci_write_config32(PCI_DEV(0, 0, 0), 0x74, 0x02006056);
        pci_write_config32(PCI_DEV(0, 0, 0), 0x78, 0x00800001);
        */
-       pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, 0x00000001); 
-       
+       pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, 0x00000001);
+
        pci_write_config32(PCI_DEV(0, 0, 0), 0xbc, 0x00001020);
        /*
        pci_write_config32(PCI_DEV(0, 0, 0), 0xfc, 0x00000109);
        */
 
        /* 0:0.1 */
-       pci_write_config32(ctrl->d0, 0x74, 0x00000001); 
+       pci_write_config32(ctrl->d0, 0x74, 0x00000001);
        pci_write_config32(ctrl->d0, 0x78, 0x001fe974);
        pci_write_config32(ctrl->d0, 0x80, 0x00af0039);
        pci_write_config32(ctrl->d0, 0x84, 0x0000033c);
@@ -133,7 +133,7 @@ static void spd_set_undocumented_registers(const struct mem_controller *ctrl)
        pci_write_config32(ctrl->d0, 0xb8, 0x000055d4);
        pci_write_config32(ctrl->d0, 0xbc, 0x024acd38);
        pci_write_config32(ctrl->d0, 0xc0, 0x00000003);
-       
+
        /* 0:0.3 */
        /*
        pci_write_config32(PCI_DEV(0, 0, 3), 0x2c, 0x35858086);
@@ -147,12 +147,12 @@ static void spd_set_undocumented_registers(const struct mem_controller *ctrl)
        pci_write_config32(PCI_DEV(0, 0, 3), 0x7c, 0x0284007f);
        pci_write_config32(PCI_DEV(0, 0, 3), 0x84, 0x000000ef);
        */
-       
+
        /*
        pci_write_config16(PCI_DEV(0, 0, 3), 0xc0, 0x0200);
        pci_write_config16(PCI_DEV(0, 0, 3), 0xc0, 0x0400);
        */
-       
+
        /*
        pci_write_config32(PCI_DEV(0, 0, 3), 0xc4, 0x00000000);
        pci_write_config32(PCI_DEV(0, 0, 3), 0xd8, 0xff00c308);
@@ -180,7 +180,7 @@ static void ram_command(const struct mem_controller *ctrl,
                        uint32_t addr)
 {
        uint32_t drc_reg;
-       
+
        drc_reg = pci_read_config32(ctrl->d0, 0x70);
        drc_reg &= ~(7 << 4);
        drc_reg |= (command << 4);
@@ -195,12 +195,12 @@ static void ram_command_mrs(const struct mem_controller *ctrl,
 {
        uint32_t drc_reg;
        uint32_t adjusted_mode;
-       
+
        drc_reg = pci_read_config32(ctrl->d0, 0x70);
        drc_reg &= ~(7 << 4);
        drc_reg |= (command << 4);
        pci_write_config8(ctrl->d0, 0x70, drc_reg);
-       /* Host address lines [13:3] map to DIMM address lines [11, 9:0] */     
+       /* Host address lines [13:3] map to DIMM address lines [11, 9:0] */
        adjusted_mode = ((mode & 0x800) << (13 - 11)) | ((mode & 0x3ff) << (12 - 9));
        print_debug("Setting mode: ");
        print_debug_hex32(adjusted_mode + addr);
@@ -211,7 +211,7 @@ static void ram_command_mrs(const struct mem_controller *ctrl,
 static void set_initialize_complete(const struct mem_controller *ctrl)
 {
        uint32_t drc_reg;
-       
+
        drc_reg = pci_read_config32(ctrl->d0, 0x70);
        drc_reg |= (1 << 29);
        pci_write_config32(ctrl->d0, 0x70, drc_reg);
@@ -224,7 +224,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
        print_debug("Ram enable 1\n");
        delay();
        delay();
-       
+
        print_debug("Ram enable 2\n");
        ram_command(ctrl, 1, 0);
        ram_command(ctrl, 1, rank1);
@@ -242,17 +242,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
        ram_command_mrs(ctrl, 4, SDRAM_EXTMODE_DLL_ENABLE, rank1);
        delay();
        delay();
-       
+
        print_debug("Ram enable 5\n");
        ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_DLL_RESET, 0);
        ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_DLL_RESET, rank1);
-       
+
        print_debug("Ram enable 6\n");
        ram_command(ctrl, 2, 0);
        ram_command(ctrl, 2, rank1);
        delay();
        delay();
-       
+
        print_debug("Ram enable 7\n");
        for(i = 0; i < 8; i++) {
                ram_command(ctrl, 6, 0);
@@ -270,19 +270,19 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
        ram_command(ctrl, 7, rank1);
        delay();
        delay();
-       
+
        print_debug("Ram enable 9\n");
        set_initialize_complete(ctrl);
-       
+
        delay();
        delay();
        delay();
-       
+
        print_debug("After configuration:\n");
        /* dump_pci_devices(); */
-       
+
        /*
-       print_debug("\n\n***** RAM TEST *****\n");      
+       print_debug("\n\n***** RAM TEST *****\n");
        ram_check(0, 0xa0000);
        ram_check(0x100000, 0x40000000);
        */