* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
*/
#include <cpu/x86/mtrr.h>
#include <stdlib.h>
#include "raminit.h"
#include "e7520.h"
+#include <pc80/mc146818rtc.h>
+#if CONFIG_HAVE_OPTION_TABLE
+#include "option_table.h"
+#endif
#define BAR 0x40000000
print_spew("done.\n");
}
-
-
struct dimm_size {
unsigned long side1;
unsigned long side2;
hw_err:
sz.side1 = 0;
sz.side2 = 0;
- out:
+out:
return sz;
}
return 0;
}
-
static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
{
unsigned dimm_mask;
return dimm_mask;
}
-
static int spd_set_row_attributes(const struct mem_controller *ctrl,
long dimm_mask)
{
/* If an hw_error occurs report that I have no memory */
hw_err:
dra = 0;
- out:
+out:
return dra;
}
-
static int spd_set_drt_attributes(const struct mem_controller *ctrl,
long dimm_mask, uint32_t drc)
{
}
ecc = 2;
- if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) {
+#if CONFIG_HAVE_OPTION_TABLE
+ if (read_option(ECC_memory, 1) == 0) {
ecc = 0; /* ECC off in CMOS so disable it */
print_debug("ECC off\n");
- }
- else {
+ } else
+#endif
+ {
print_debug("ECC on\n");
}
drc &= ~(3 << 20); /* clear the ecc bits */
/* If an hw_error occurs report that I have no memory */
hw_err:
drc = 0;
- out:
+out:
return drc;
}
}
}
}
+
static void set_receive_enable(const struct mem_controller *ctrl)
{
unsigned int i;
write32(BAR+0x154, recenb);
}
-
static void sdram_enable(int controllers, const struct mem_controller *ctrl)
{
int i;
print_debug("Starting SDRAM Enable\n");
/* 0x80 */
-#ifdef DIMM_MAP_LOGICAL
pci_write_config32(PCI_DEV(0, 0x00, 0), DRM,
- 0x00210000 | DIMM_MAP_LOGICAL);
-#else
- pci_write_config32(PCI_DEV(0, 0x00, 0), DRM, 0x00211248);
-#endif
+ 0x00210000 | CONFIG_DIMM_MAP_LOGICAL);
/* set dram type and Front Side Bus freq. */
drc = spd_set_dram_controller_mode(ctrl, mask);
if( drc == 0) {
write32(BAR+0x100, (0x83000000 | (i<<20)));
- data32 = read32(BAR+DCALCSR);
- while(data32 & 0x80000000)
- data32 = read32(BAR+DCALCSR);
+ do data32 = read32(BAR+DCALCSR);
+ while(data32 & 0x80000000);
}
for(cs=0;cs<8;cs++) {
write32(BAR + DCALCSR, (0x83000000 | (cs<<20)));
- data32 = read32(BAR+DCALCSR);
- while(data32 & 0x80000000)
- data32 = read32(BAR+DCALCSR);
+ do data32 = read32(BAR+DCALCSR);
+ while(data32 & 0x80000000);
}
/* Precharg all banks */
else /* DDR1 */
write32(BAR+DCALADDR, 0x00000000);
write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
- data32 = read32(BAR+DCALCSR);
- while(data32 & 0x80000000)
- data32 = read32(BAR+DCALCSR);
+ do data32 = read32(BAR+DCALCSR);
+ while(data32 & 0x80000000);
}
/* EMRS dll's enabled */
else /* DDR1 */
write32(BAR+DCALADDR, 0x00000001);
write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
- data32 = read32(BAR+DCALCSR);
- while(data32 & 0x80000000)
- data32 = read32(BAR+DCALCSR);
+ do data32 = read32(BAR+DCALCSR);
+ while(data32 & 0x80000000);
}
/* MRS reset dll's */
do_delay();
for(cs=0;cs<8;cs++) {
write32(BAR+DCALADDR, mode_reg);
write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
- data32 = read32(BAR+DCALCSR);
- while(data32 & 0x80000000)
- data32 = read32(BAR+DCALCSR);
+ do data32 = read32(BAR+DCALCSR);
+ while(data32 & 0x80000000);
}
/* Precharg all banks */
else /* DDR1 */
write32(BAR+DCALADDR, 0x00000000);
write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
- data32 = read32(BAR+DCALCSR);
- while(data32 & 0x80000000)
- data32 = read32(BAR+DCALCSR);
+ do data32 = read32(BAR+DCALCSR);
+ while(data32 & 0x80000000);
}
/* Do 2 refreshes */
do_delay();
for(cs=0;cs<8;cs++) {
write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
- data32 = read32(BAR+DCALCSR);
- while(data32 & 0x80000000)
- data32 = read32(BAR+DCALCSR);
+ do data32 = read32(BAR+DCALCSR);
+ while(data32 & 0x80000000);
}
do_delay();
for(cs=0;cs<8;cs++) {
write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
- data32 = read32(BAR+DCALCSR);
- while(data32 & 0x80000000)
- data32 = read32(BAR+DCALCSR);
+ do data32 = read32(BAR+DCALCSR);
+ while(data32 & 0x80000000);
}
do_delay();
/* for good luck do 6 more */
for(cs=0;cs<8;cs++) {
write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
- data32 = read32(BAR+DCALCSR);
- while(data32 & 0x80000000)
- data32 = read32(BAR+DCALCSR);
+ do data32 = read32(BAR+DCALCSR);
+ while(data32 & 0x80000000);
}
/* Do only if DDR2 EMRS dll's enabled */
for(cs=0;cs<8;cs++) {
write32(BAR+DCALADDR, (0x0b940001));
write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
- data32 = read32(BAR+DCALCSR);
- while(data32 & 0x80000000)
- data32 = read32(BAR+DCALCSR);
+ do data32 = read32(BAR+DCALCSR);
+ while(data32 & 0x80000000);
}
}
for(cs=0;cs<8;cs++) {
write32(BAR+DCALCSR, (0x830831d8 | (cs<<20)));
- data32 = read32(BAR+DCALCSR);
- while(data32 & 0x80000000)
- data32 = read32(BAR+DCALCSR);
+ do data32 = read32(BAR+DCALCSR);
+ while(data32 & 0x80000000);
}
/* Bring memory subsystem on line */