Move C labels to start-of-line

[coreboot.git] / src / northbridge / intel / e7520 / raminit.c

diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c
index 6eed1964e9ef82bf0ec068cabf6c006ef8e20e1e..d226085d0d834cb86ad47c571f323b3ee95f169b 100644 (file)
--- a/src/northbridge/intel/e7520/raminit.c
+++ b/src/northbridge/intel/e7520/raminit.c
@@ -161,7 +161,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device)
 hw_err:
        sz.side1 = 0;
        sz.side2 = 0;
- out:
+out:
        return sz;
 
 }
@@ -286,7 +286,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
        /* If an hw_error occurs report that I have no memory */
 hw_err:
        dra = 0;
- out:
+out:
        return dra;
 
 }
@@ -618,7 +618,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
        }
        ecc = 2;
 #if CONFIG_HAVE_OPTION_TABLE
-       if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
+       if (read_option(ECC_memory, 1) == 0) {
                ecc = 0;  /* ECC off in CMOS so disable it */
                print_debug("ECC off\n");
        } else
@@ -658,7 +658,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
        /* If an hw_error occurs report that I have no memory */
 hw_err:
        drc = 0;
- out:
+out:
        return drc;
 }
 
@@ -1128,9 +1128,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
                write32(BAR+0x100, (0x83000000 | (i<<20)));
 
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
 
        }
 
@@ -1139,9 +1138,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
        for(cs=0;cs<8;cs++) {
                write32(BAR + DCALCSR, (0x83000000 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Precharg all banks */
@@ -1152,9 +1150,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000000);
                write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* EMRS dll's enabled */
@@ -1166,9 +1163,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000001);
                write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
        /* MRS reset dll's */
        do_delay();
@@ -1187,9 +1183,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
        for(cs=0;cs<8;cs++) {
                write32(BAR+DCALADDR, mode_reg);
                write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Precharg all banks */
@@ -1202,25 +1197,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000000);
                write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Do 2 refreshes */
        do_delay();
        for(cs=0;cs<8;cs++) {
                write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
        do_delay();
        for(cs=0;cs<8;cs++) {
                write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
        do_delay();
        /* for good luck do 6 more */
@@ -1253,9 +1245,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
        for(cs=0;cs<8;cs++) {
                write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
                write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Do only if DDR2  EMRS dll's enabled */
@@ -1264,9 +1255,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 for(cs=0;cs<8;cs++) {
                         write32(BAR+DCALADDR, (0x0b940001));
                         write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-                       data32 = read32(BAR+DCALCSR);
-                       while(data32 & 0x80000000)
-                               data32 = read32(BAR+DCALCSR);
+                       do data32 = read32(BAR+DCALCSR);
+                       while(data32 & 0x80000000);
                 }
         }
 
@@ -1310,9 +1300,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
        for(cs=0;cs<8;cs++) {
                write32(BAR+DCALCSR, (0x830831d8 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Bring memory subsystem on line */