/* for PCI_ADDR(0, 0x18, 2, 0x98) index,
and PCI_ADDR(0x, 0x18, 2, 0x9c) data */
/*
- index:
+index:
[29: 0] DctOffset (Dram Controller Offset)
[30:30] DctAccessWrite (Dram Controller Read/Write Select)
0 = read access
/* for PCI_ADDR(0, 0x18, 2, 0x98) index,
and PCI_ADDR(0x, 0x18, 2, 0x9c) data */
/*
- index:
+index:
[29: 0] DctOffset (Dram Controller Offset)
[30:30] DctAccessWrite (Dram Controller Read/Write Select)
0 = read access
sz->col = 0;
sz->bank = 0;
sz->rank = 0;
- out:
+out:
return;
}