#include <stdlib.h>
#include "raminit.h"
-#include "amdk8_f.h"
+#include "f.h"
#include <spd_ddr2.h>
-
-#ifndef QRANK_DIMM_SUPPORT
-#define QRANK_DIMM_SUPPORT 0
+#if CONFIG_HAVE_OPTION_TABLE
+#include "option_table.h"
#endif
#if CONFIG_DEBUG_RAM_SETUP
-#define printk_raminit(fmt, arg...) printk(BIOS_DEBUG, fmt, arg)
+#define printk_raminit(args...) printk(BIOS_DEBUG, args)
#else
-#define printk_raminit(fmt, arg...)
+#define printk_raminit(args...)
#endif
# error "CONFIG_RAMTOP must be a power of 2"
#endif
-#include "amdk8_f_pci.c"
+#include "f_pci.c"
/* for PCI_ADDR(0, 0x18, 2, 0x98) index,
*/
-static void setup_resource_map(const unsigned int *register_values, int max)
+void setup_resource_map(const unsigned int *register_values, int max)
{
int i;
for (i = 0; i < max; i += 3) {
* 110 = 8 bus clocks
* 111 = 9 bus clocks
* [ 7: 7] Reserved
- * [ 9: 8] Twtr (Internal DRAM Write-to-Read Command Delay,
+ * [ 9: 8] Twtr (Internal DRAM Write-to-Read Command Delay,
* minium write-to-read delay when both access the same chip select)
* 00 = Reserved
* 01 = 1 bus clocks
* registered DIMM is present
* [19:19] Reserved
* [20:20] SlowAccessMode (Slow Access Mode (2T Mode))
- * 0 = DRAM address and control signals are driven for one
+ * 0 = DRAM address and control signals are driven for one
* MEMCLK cycle
* 1 = One additional MEMCLK of setup time is provided on all
* DRAM address and control signals except CS, CKE, and ODT;
{
/* Test to see if I am an Opteron. M2 and S1G1 support dual
* channel, too, but only support unbuffered DIMMs so we need a
- * better test for Opterons.
+ * better test for Opterons.
* However, all code uses is_opteron() to find out whether to
* use dual channel, so if we really check for opteron here, we
* need to fix up all code using this function, too.
/* Set the appropriate DIMM base address register */
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), base0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), base1);
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
if (sz->rank == 4) {
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), base0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), base1);
} else {
dword = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); //Channel A
dword &= ~(ClkDis0 >> index);
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
if (sz->rank == 4) {
dword &= ~(ClkDis0 >> (index+2));
}
if (meminfo->is_Width128) { // ChannelA+B
dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
dword &= ~(ClkDis0 >> index);
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
if (sz->rank == 4) {
dword &= ~(ClkDis0 >> (index+2));
}
}
map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
map &= ~(0xf << (index * 4));
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
if (sz->rank == 4) {
map &= ~(0xf << ( (index + 2) * 4));
}
unsigned temp_map;
temp_map = cs_map_aaa[(sz->bank-2)*3*4 + (sz->rows - 13)*3 + (sz->col - 9) ];
map |= temp_map << (index*4);
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
if (sz->rank == 4) {
map |= temp_map << ( (index + 2) * 4);
}
/* See if all of the memory chip selects are the same size
* and if so count them.
*/
+#if defined(CMOS_VSTART_interleave_chip_selects)
+ if (read_option(interleave_chip_selects, 1) == 0)
+ return 0;
+#else
+#if !defined(CONFIG_INTERLEAVE_CHIP_SELECTS) || !CONFIG_INTERLEAVE_CHIP_SELECTS
+ return 0;
+#endif
+#endif
+
chip_selects = 0;
common_size = 0;
common_cs_mode = 0xff;
csbase = value;
canidate = index;
}
-
+
/* See if I have found a new canidate */
if (csbase == 0) {
break;
{
unsigned long tom_k, base_k;
- if (read_option(CMOS_VSTART_interleave_chip_selects,
- CMOS_VLEN_interleave_chip_selects, 1) != 0) {
- tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128);
- } else {
- printk(BIOS_DEBUG, "Interleaving disabled\n");
- tom_k = 0;
- }
+ tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128);
if (!tom_k) {
+ printk(BIOS_DEBUG, "Interleaving disabled\n");
tom_k = order_chip_selects(ctrl);
}
} else {
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), 0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), 0);
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
if (meminfo->sz[index].rank == 4) {
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0);
/*15*/ 200, 160, 120, 100,
};
-
+
int index;
msr_t msr;
unsigned fid_start;
msr = rdmsr(0xc0010015);
fid_start = (msr.lo & (0x3f << 24));
-
+
index = fid_start>>25;
}
value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
bios_cycle_time = min_cycle_times[
- read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)];
+#ifdef CMOS_VSTART_max_mem_clock
+ read_option(max_mem_clock, 0)
+#else
+#if defined(CONFIG_MAX_MEM_CLOCK)
+ CONFIG_MAX_MEM_CLOCK
+#else
+ 0 // use DDR400 as default
+#endif
+#endif
+ ];
+
if (bios_cycle_time > min_cycle_time) {
min_cycle_time = bios_cycle_time;
}
continue;
}
}
-
+
}
/* Make a second pass through the dimms and disable
* any that cannot support the selected memclk and cas latency.
if (clocks < TT_MIN) {
clocks = TT_MIN;
}
-
+
if (clocks > TT_MAX) {
printk(BIOS_INFO, "warning spd byte : %x = %x > TT_MAX: %x, setting TT_MAX", SPD_TT, value, TT_MAX);
clocks = TT_MAX;
static void set_4RankRDimm(const struct mem_controller *ctrl,
const struct mem_param *param, struct mem_info *meminfo)
{
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
int value;
int i;
long dimm_mask = meminfo->dimm_mask;
uint32_t mask_single_rank;
uint32_t mask_page_1k;
int value;
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
int rank;
#endif
value = spd_read_byte(spd_device, SPD_PRI_WIDTH);
- #if QRANK_DIMM_SUPPORT == 1
+ #if CONFIG_QRANK_DIMM_SUPPORT
rank = meminfo->sz[i].rank;
#endif
if (value==4) {
mask_x4 |= (1<<i);
- #if QRANK_DIMM_SUPPORT == 1
+ #if CONFIG_QRANK_DIMM_SUPPORT
if (rank==4) {
mask_x4 |= 1<<(i+2);
}
#endif
} else if (value==16) {
mask_x16 |= (1<<i);
- #if QRANK_DIMM_SUPPORT == 1
+ #if CONFIG_QRANK_DIMM_SUPPORT
if (rank==4) {
mask_x16 |= 1<<(i+2);
}
if (nbcap & NBCAP_ECC) {
dcl |= DCL_DimmEccEn;
}
- if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
+#ifdef CMOS_VSTART_ECC_memory
+ if (read_option(ECC_memory, 1) == 0) {
dcl &= ~DCL_DimmEccEn;
}
+#else // CMOS_VSTART_ECC_memory not defined
+#if !CONFIG_ECC_MEMORY
+ dcl &= ~DCL_DimmEccEn;
+#endif
+#endif
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
meminfo->is_ecc = 1;
if (!(dcl & DCL_DimmEccEn)) {
meminfo->is_ecc = 0;
+ printk(BIOS_DEBUG, "set_ecc: ECC disabled\n");
return; // already disabled the ECC, so don't need to read SPD any more
}
uint32_t reg;
if ((val < TT_MIN) || (val > TT_MAX)) {
- printk(BIOS_ERR, str);
+ printk(BIOS_ERR, "%s", str);
die(" Unknown\n");
}
unsigned SlowAccessMode = 0;
#endif
- long dimm_mask = meminfo->dimm_mask & 0x0f;
-
#if CONFIG_DIMM_SUPPORT==0x0104 /* DDR2 and REG */
+ long dimm_mask = meminfo->dimm_mask & 0x0f;
/* for REG DIMM */
dword = 0x00111222;
dwordx = 0x002f0000;
#endif
#if CONFIG_DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */
+ long dimm_mask = meminfo->dimm_mask & 0x0f;
/* for UNBUF DIMM */
dword = 0x00111222;
dwordx = 0x002f2f00;
}
#endif
-
+#if CONFIG_HAVE_ACPI_RESUME == 1
#include "exit_from_self.c"
+#endif
static void sdram_enable(int controllers, const struct mem_controller *ctrl,
struct sys_info *sysinfo)
{
int i;
-#ifdef ACPI_IS_WAKEUP_EARLY
+#if CONFIG_HAVE_ACPI_RESUME == 1
int suspend = acpi_is_wakeup_early();
#else
int suspend = 0;
#endif
-
+
#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
unsigned cpu_f0_f1[8];
/* FIXME: How about 32 node machine later? */
}
-static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
+void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
const uint16_t *spd_addr)
{
int i;