remove trailing whitespace

[coreboot.git] / src / northbridge / amd / amdk8 / misc_control.c

diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c
index 1b40eb1381b2eaf47cd4fe7e9756e6e30dcae25a..7ba2b90406b8462b32030f2842fbadf29d4eaf9b 100644 (file)
--- a/src/northbridge/amd/amdk8/misc_control.c
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -1,10 +1,10 @@
 /* Turn off machine check triggers when reading
- * pci space where there are no devices.
- * This is necessary when scaning the bus for
+ * PCI space where there are no devices.
+ * This is necessary when scanning the bus for
  * devices which is done by the kernel
  *
  * written in 2003 by Eric Biederman
- * 
+ *
  *  - Athlon64 workarounds by Stefan Reinauer
  *  - "reset once" logic by Yinghai Lu
  */
@@ -24,15 +24,15 @@
 /**
  * @brief Read resources for AGP aperture
  *
- * @param 
+ * @param
  *
- * There is only one AGP aperture resource needed. The resoruce is added to
+ * There is only one AGP aperture resource needed. The resource is added to
  * the northbridge of BSP.
  *
  * The same trick can be used to augment legacy VGA resources which can
- * be detect by generic pci reousrce allocator for VGA devices.
+ * be detect by generic PCI resource allocator for VGA devices.
  * BAD: it is more tricky than I think, the resource allocation code is
- * implemented in a way to NOT DOING legacy VGA resource allcation on
+ * implemented in a way to NOT DOING legacy VGA resource allocation on
  * purpose :-(.
  */
 static void mcf3_read_resources(device_t dev)
@@ -42,16 +42,19 @@ static void mcf3_read_resources(device_t dev)
        /* Read the generic PCI resources */
        pci_dev_read_resources(dev);
 
-       /* If we are not the first processor don't allocate the gart apeture */
+       /* If we are not the first processor don't allocate the GART aperture */
        if (dev->path.pci.devfn != PCI_DEVFN(0x18, 3)) {
                return;
        }
 
        iommu = 1;
-       get_option(&iommu, "iommu");
+       if( get_option(&iommu, "iommu") < 0 )
+       {
+               iommu = CONFIG_IOMMU;
+       }
 
        if (iommu) {
-               /* Add a Gart apeture resource */
+               /* Add a GART aperture resource */
                resource = new_resource(dev, 0x94);
                resource->size = CONFIG_AGP_APERTURE_SIZE;
                resource->align = log2(resource->size);
@@ -64,7 +67,7 @@ static void mcf3_read_resources(device_t dev)
 static void set_agp_aperture(device_t dev)
 {
        struct resource *resource;
-               
+
        resource = probe_resource(dev, 0x94);
        if (resource) {
                device_t pdev;
@@ -78,8 +81,8 @@ static void set_agp_aperture(device_t dev)
 
                /* Get the base address */
                gart_base = ((resource->base) >> 25) & 0x00007fff;
-               
-               /* Update the other northbriges */
+
+               /* Update the other northbridges */
                pdev = 0;
                while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) {
                        /* Store the GART size but don't enable it */
@@ -90,7 +93,7 @@ static void set_agp_aperture(device_t dev)
 
                        /* Don't set the GART Table base address */
                        pci_write_config32(pdev, 0x98, 0);
-                       
+
                        /* Report the resource has been stored... */
                        report_resource_stored(pdev, resource, " <gart>");
                }
@@ -110,8 +113,8 @@ static void misc_control_init(struct device *dev)
 {
        uint32_t cmd, cmd_ref;
        int needs_reset;
-       struct device *f0_dev, *f2_dev;
-       
+       struct device *f0_dev;
+
        printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. ");
        needs_reset = 0;
 
@@ -125,7 +128,7 @@ static void misc_control_init(struct device *dev)
        if (is_cpu_pre_c0()) {
 
                /* Errata 58
-                * Disable CPU low power states C2, C1 and throttling 
+                * Disable CPU low power states C2, C1 and throttling
                 */
                cmd = pci_read_config32(dev, 0x80);
                cmd &= ~(1<<0);
@@ -136,7 +139,7 @@ static void misc_control_init(struct device *dev)
                pci_write_config32(dev, 0x84, cmd );
 
                /* Errata 66
-                * Limit the number of downstream posted requests to 1 
+                * Limit the number of downstream posted requests to 1
                 */
                cmd = pci_read_config32(dev, 0x70);
                if ((cmd & (3 << 0)) != 2) {
@@ -161,9 +164,10 @@ static void misc_control_init(struct device *dev)
                }
        }
        else if(is_cpu_pre_d0()) {
+               struct device *f2_dev;
                uint32_t dcl;
                f2_dev = dev_find_slot(0, dev->path.pci.devfn - 3 + 2);
-               /* Errata 98 
+               /* Errata 98
                 * Set Clk Ramp Hystersis to 7
                 * Clock Power/Timing Low
                 */
@@ -191,7 +195,7 @@ static void misc_control_init(struct device *dev)
                        reg = 0x98 + (link * 0x20);
                        link_type = pci_read_config32(f0_dev, reg);
                        /* Only handle coherent link here please */
-                       if ((link_type & (LinkConnected|InitComplete|NonCoherent)) 
+                       if ((link_type & (LinkConnected|InitComplete|NonCoherent))
                                == (LinkConnected|InitComplete))
                        {
                                cmd &= ~(0xff << (link *8));