#include <device/hypertransport_def.h>
#include <stdlib.h>
#include "arch/romcc_io.h"
+#include <pc80/mc146818rtc.h>
+#if CONFIG_HAVE_OPTION_TABLE
+#include "option_table.h"
+#endif
#include "amdk8.h"
#define TRY_HIGH_FIRST 0
#endif
-#ifndef K8_HT_FREQ_1G_SUPPORT
- #define K8_HT_FREQ_1G_SUPPORT 0
+#ifndef CONFIG_K8_HT_FREQ_1G_SUPPORT
+ #define CONFIG_K8_HT_FREQ_1G_SUPPORT 0
#endif
#ifndef K8_HT_CHECK_PENDING_LINK
#define CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED 0
#endif
-#ifndef ENABLE_APIC_EXT_ID
- #define ENABLE_APIC_EXT_ID 0
+#ifndef CONFIG_ENABLE_APIC_EXT_ID
+ #define CONFIG_ENABLE_APIC_EXT_ID 0
#endif
static inline void print_linkn (const char *strval, uint8_t byteval)
{
-#if 1
-#if CONFIG_USE_PRINTK_IN_CAR
- printk_debug("%s%02x\r\n", strval, byteval);
-#else
- print_debug(strval); print_debug_hex8(byteval); print_debug("\r\n");
-#endif
-#endif
+ printk(BIOS_DEBUG, "%s%02x\n", strval, byteval);
}
static void disable_probes(void)
HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P;
pci_write_config32(NODE_HT(0), HT_TRANSACTION_CONTROL, val);
- print_spew("done.\r\n");
+ print_spew("done.\n");
}
+#if 0
static void enable_apic_ext_id(u8 node)
{
-#if ENABLE_APIC_EXT_ID==1
+#if CONFIG_ENABLE_APIC_EXT_ID==1
#warning "FIXME Is the right place to enable apic ext id here?"
u32 val;
pci_write_config32(NODE_HT(node), 0x68, val);
#endif
}
+#endif
static void enable_routing(u8 node)
{
val &= ~((1<<1)|(1<<0));
pci_write_config32(NODE_HT(node), 0x6c, val);
- print_spew(" done.\r\n");
+ print_spew(" done.\n");
}
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
static void fill_row(u8 node, u8 row, u32 value)
{
pci_write_config32(NODE_HT(node), 0x40+(row<<2), value);
}
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
static u8 link_to_register(int ldt)
{
/*
val |= node; /* new node */
pci_write_config32(NODE_HT(7), 0x60, val);
- print_spew(" done.\r\n");
+ print_spew(" done.\n");
}
static int verify_connection(u8 dest)
freq_cap = pci_read_config16(dev, pos);
freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
-#if K8_HT_FREQ_1G_SUPPORT == 1
- #if K8_REV_F_SUPPORT == 0
+#if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1
+ #if CONFIG_K8_REV_F_SUPPORT == 0
if (!is_cpu_pre_e0())
#endif
{
return byte;
}
+#if TRY_HIGH_FIRST == 1
static uint8_t get_linkn_last(uint8_t byte)
{
if(byte & 0x02) { byte &= 0x0f; byte |= 0x00; }
if(byte & 0x08) { byte &= 0x0f; byte |= 0x20; }
return byte>>4;
}
+#endif
+#if (CONFIG_MAX_PHYSICAL_CPUS > 2) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
static uint8_t get_linkn_last_count(uint8_t byte)
{
byte &= 0x0f;
if(byte & 0x08) { byte &= 0xcf; byte |= 0x20; byte+=0x40; }
return byte>>4;
}
+#endif
static void setup_row_local(u8 source, u8 row) /* source will be 7 when it is for temp use*/
{
}
#if CROSS_BAR_47_56
-static void opt_broadcast_rt(u8 source, u8 dest, u8 kickout) {
+static void opt_broadcast_rt(u8 source, u8 dest, u8 kickout)
+{
uint32_t val;
val = get_row(source, dest);
val -= link_connection(source, kickout)<<16;
fill_row(source, dest, val);
}
-static void opt_broadcast_rt_group(const u8 *conn, int num) {
+static void opt_broadcast_rt_group(const u8 *conn, int num)
+{
int i;
for(i=0; i<num; i+=3) {
opt_broadcast_rt(conn[i], conn[i+1],conn[i+2]);
}
}
-static void opt_broadcast_rt_plus(u8 source, u8 dest, u8 kickout) {
+
+static void opt_broadcast_rt_plus(u8 source, u8 dest, u8 kickout)
+{
uint32_t val;
val = get_row(source, dest);
val += link_connection(source, kickout)<<16;
fill_row(source, dest, val);
}
-static void opt_broadcast_rt_plus_group(const u8 *conn, int num) {
+static void opt_broadcast_rt_plus_group(const u8 *conn, int num)
+{
int i;
for(i=0; i<num; i+=3) {
}
#endif
-static void setup_row_direct(u8 source, u8 dest, u8 linkn){
+static void setup_row_direct(u8 source, u8 dest, u8 linkn)
+{
setup_row_direct_x(source, source, dest, linkn);
}
-static void setup_remote_row_direct(u8 source, u8 dest, u8 linkn){
+static void setup_remote_row_direct(u8 source, u8 dest, u8 linkn)
+{
setup_row_direct_x(7, source, dest, linkn);
}
static void setup_temp_row(u8 source, u8 dest)
{
- /* copy val from (source, dest) to (source,7) */
- fill_row(source,7,get_row(source,dest));
-}
-
-static void clear_temp_row(u8 source)
-{
- fill_row(source, 7, DEFAULT);
+ /* copy value from (source, dest) to (source,7) */
+ fill_row(source, 7, get_row(source, dest));
}
static void setup_remote_node(u8 node)
pci_write_config32(NODE_MP(7), reg, value);
}
- print_spew("done\r\n");
+ print_spew("done\n");
}
#endif /* CONFIG_MAX_PHYSICAL_CPUS > 1*/
static void setup_uniprocessor(void)
{
- print_spew("Enabling UP settings\r\n");
+ print_spew("Enabling UP settings\n");
#if CONFIG_LOGICAL_CPUS==1
unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3;
if (tmp>0) return;
}
#if CONFIG_MAX_PHYSICAL_CPUS > 2
-static int optimize_connection_group(const u8 *opt_conn, int num) {
+static int optimize_connection_group(const u8 *opt_conn, int num)
+{
int needs_reset = 0;
int i;
for(i=0; i<num; i+=2) {
{
unsigned nodes;
- print_spew("Enabling SMP settings\r\n");
+ print_spew("Enabling SMP settings\n");
nodes = setup_smp2();
#if CONFIG_MAX_PHYSICAL_CPUS > 2
nodes = setup_smp8();
#endif
-#if CONFIG_USE_PRINTK_IN_CAR
- printk_debug("%02x nodes initialized.\r\n", nodes);
-#else
- print_debug_hex8(nodes);
- print_debug(" nodes initialized.\r\n");
-#endif
+ printk(BIOS_DEBUG, "%02x nodes initialized.\n", nodes);
return nodes;
}
#if CONFIG_MAX_PHYSICAL_CPUS > 2
case 0x02: /* MPCap */
if(nodes > 2) {
- print_err("Going back to DP\r\n");
+ print_err("Going back to DP\n");
return 2;
}
break;
#endif
case 0x00: /* Non SMP */
if(nodes >1 ) {
- print_err("Going back to UP\r\n");
+ print_err("Going back to UP\n");
return 1;
}
break;
static void coherent_ht_finalize(unsigned nodes)
{
unsigned node;
-#if K8_REV_F_SUPPORT == 0
+#if CONFIG_K8_REV_F_SUPPORT == 0
int rev_a0;
#endif
#if CONFIG_LOGICAL_CPUS==1
unsigned total_cpus;
- if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) == 0) { /* dual_core */
+ if (read_option(multi_core, 0) == 0) { /* multi_core */
total_cpus = verify_dualcore(nodes);
}
else {
* registers on Hammer A0 revision.
*/
- print_spew("coherent_ht_finalize\r\n");
-#if K8_REV_F_SUPPORT == 0
+ print_spew("coherent_ht_finalize\n");
+#if CONFIG_K8_REV_F_SUPPORT == 0
rev_a0 = is_cpu_rev_a0();
#endif
for (node = 0; node < nodes; node++) {
(3 << HTTC_HI_PRI_BYP_CNT_SHIFT);
pci_write_config32(dev, HT_TRANSACTION_CONTROL, val);
-#if K8_REV_F_SUPPORT == 0
+#if CONFIG_K8_REV_F_SUPPORT == 0
if (rev_a0) {
pci_write_config32(dev, 0x94, 0);
pci_write_config32(dev, 0xb4, 0);
#endif
}
- print_spew("done\r\n");
+ print_spew("done\n");
}
static int apply_cpu_errata_fixes(unsigned nodes)
device_t dev;
uint32_t cmd;
dev = NODE_MC(node);
-#if K8_REV_F_SUPPORT == 0
+#if CONFIG_K8_REV_F_SUPPORT == 0
if (is_cpu_pre_c0()) {
/* Errata 66
}
}
#endif
+
+
+#if CONFIG_K8_REV_F_SUPPORT == 0
+ /* I can't touch this msr on early buggy cpus, and cannot apply either 169 or 131 */
+ if (!is_cpu_pre_b3())
+#endif
+ {
+ /* Errata 169 */
+ /* We also need to set some bits in NB_CFG_MSR, which is handled in src/cpu/amd/model_fxx/ */
+ dev = NODE_HT(node);
+ cmd = pci_read_config32(dev, 0x68);
+ cmd &= ~(1 << 22);
+ cmd |= (1 << 21);
+ pci_write_config32(dev, 0x68, cmd);
+ }
}
return needs_reset;
}
return needs_reset;
}
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
static void setup_coherent_ht_domain(void)
#else
static int setup_coherent_ht_domain(void)
}
coherent_ht_finalize(nodes);
-#if RAMINIT_SYSINFO == 0
+#if !CONFIG_RAMINIT_SYSINFO
return optimize_link_coherent_ht();
#endif
}
projects / coreboot.git / blobdiff