remove trailing whitespace

[coreboot.git] / src / northbridge / amd / amdk8 / coherent_ht.c

diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 30e047134792828fe79368cb8d207a01c12d2602..a262686f871609d5643c479c92775f1730a33e90 100644 (file)
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -673,7 +673,7 @@ static void setup_uniprocessor(void)
 }
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 2
-static int optimize_connection_group(const u8 *opt_conn, int num) 
+static int optimize_connection_group(const u8 *opt_conn, int num)
 {
        int needs_reset = 0;
        int i;
@@ -1599,7 +1599,7 @@ static void coherent_ht_finalize(unsigned nodes)
 #if CONFIG_LOGICAL_CPUS==1
        unsigned total_cpus;
 
-       if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) == 0) { /* multi_core */
+       if (read_option(multi_core, 0) == 0) { /* multi_core */
                total_cpus = verify_dualcore(nodes);
        }
        else {
@@ -1662,10 +1662,10 @@ static int apply_cpu_errata_fixes(unsigned nodes)
        unsigned node;
        int needs_reset = 0;
        for(node = 0; node < nodes; node++) {
-#if CONFIG_K8_REV_F_SUPPORT == 0
                device_t dev;
                uint32_t cmd;
                dev = NODE_MC(node);
+#if CONFIG_K8_REV_F_SUPPORT == 0
                if (is_cpu_pre_c0()) {
 
                        /* Errata 66
@@ -1708,6 +1708,21 @@ static int apply_cpu_errata_fixes(unsigned nodes)
                        }
                }
 #endif
+
+
+#if CONFIG_K8_REV_F_SUPPORT == 0
+               /* I can't touch this msr on early buggy cpus, and cannot apply either 169 or 131 */
+               if (!is_cpu_pre_b3())
+#endif
+               {
+                       /* Errata 169 */
+                       /* We also need to set some bits in NB_CFG_MSR, which is handled in src/cpu/amd/model_fxx/ */
+                       dev = NODE_HT(node);
+                       cmd = pci_read_config32(dev, 0x68);
+                       cmd &= ~(1 << 22);
+                       cmd |= (1 << 21);
+                       pci_write_config32(dev, 0x68, cmd);
+               }
        }
        return needs_reset;
 }