#include <stdlib.h>
#include "arch/romcc_io.h"
#include <pc80/mc146818rtc.h>
+#if CONFIG_HAVE_OPTION_TABLE
+#include "option_table.h"
+#endif
#include "amdk8.h"
print_spew(" done.\n");
}
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
static void fill_row(u8 node, u8 row, u32 value)
{
pci_write_config32(NODE_HT(node), 0x40+(row<<2), value);
}
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
static u8 link_to_register(int ldt)
{
/*
}
#if CROSS_BAR_47_56
-static void opt_broadcast_rt(u8 source, u8 dest, u8 kickout) {
+static void opt_broadcast_rt(u8 source, u8 dest, u8 kickout)
+{
uint32_t val;
val = get_row(source, dest);
val -= link_connection(source, kickout)<<16;
fill_row(source, dest, val);
}
-static void opt_broadcast_rt_group(const u8 *conn, int num) {
+static void opt_broadcast_rt_group(const u8 *conn, int num)
+{
int i;
for(i=0; i<num; i+=3) {
opt_broadcast_rt(conn[i], conn[i+1],conn[i+2]);
}
}
-static void opt_broadcast_rt_plus(u8 source, u8 dest, u8 kickout) {
+
+static void opt_broadcast_rt_plus(u8 source, u8 dest, u8 kickout)
+{
uint32_t val;
val = get_row(source, dest);
val += link_connection(source, kickout)<<16;
fill_row(source, dest, val);
}
-static void opt_broadcast_rt_plus_group(const u8 *conn, int num) {
+static void opt_broadcast_rt_plus_group(const u8 *conn, int num)
+{
int i;
for(i=0; i<num; i+=3) {
}
#endif
-static void setup_row_direct(u8 source, u8 dest, u8 linkn){
+static void setup_row_direct(u8 source, u8 dest, u8 linkn)
+{
setup_row_direct_x(source, source, dest, linkn);
}
-static void setup_remote_row_direct(u8 source, u8 dest, u8 linkn){
+static void setup_remote_row_direct(u8 source, u8 dest, u8 linkn)
+{
setup_row_direct_x(7, source, dest, linkn);
}
static void setup_temp_row(u8 source, u8 dest)
{
- /* copy val from (source, dest) to (source,7) */
- fill_row(source,7,get_row(source,dest));
-}
-
-#if 0
-static void clear_temp_row(u8 source)
-{
- fill_row(source, 7, DEFAULT);
+ /* copy value from (source, dest) to (source,7) */
+ fill_row(source, 7, get_row(source, dest));
}
-#endif
static void setup_remote_node(u8 node)
{
}
#if CONFIG_MAX_PHYSICAL_CPUS > 2
-static int optimize_connection_group(const u8 *opt_conn, int num) {
+static int optimize_connection_group(const u8 *opt_conn, int num)
+{
int needs_reset = 0;
int i;
for(i=0; i<num; i+=2) {
#if CONFIG_LOGICAL_CPUS==1
unsigned total_cpus;
- if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) == 0) { /* multi_core */
+ if (read_option(multi_core, 0) == 0) { /* multi_core */
total_cpus = verify_dualcore(nodes);
}
else {
unsigned node;
int needs_reset = 0;
for(node = 0; node < nodes; node++) {
-#if CONFIG_K8_REV_F_SUPPORT == 0
device_t dev;
uint32_t cmd;
dev = NODE_MC(node);
+#if CONFIG_K8_REV_F_SUPPORT == 0
if (is_cpu_pre_c0()) {
/* Errata 66
}
}
#endif
+
+
+#if CONFIG_K8_REV_F_SUPPORT == 0
+ /* I can't touch this msr on early buggy cpus, and cannot apply either 169 or 131 */
+ if (!is_cpu_pre_b3())
+#endif
+ {
+ /* Errata 169 */
+ /* We also need to set some bits in NB_CFG_MSR, which is handled in src/cpu/amd/model_fxx/ */
+ dev = NODE_HT(node);
+ cmd = pci_read_config32(dev, 0x68);
+ cmd &= ~(1 << 22);
+ cmd |= (1 << 21);
+ pci_write_config32(dev, 0x68, cmd);
+ }
}
return needs_reset;
}
return needs_reset;
}
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
static void setup_coherent_ht_domain(void)
#else
static int setup_coherent_ht_domain(void)
}
coherent_ht_finalize(nodes);
-#if RAMINIT_SYSINFO == 0
+#if !CONFIG_RAMINIT_SYSINFO
return optimize_link_coherent_ht();
#endif
}