Find matching settings for each CPUs FID, VID, and P-state registers and initialize...

[coreboot.git] / src / northbridge / amd / amdht / AsPsDefs.h

diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h
index 62b7edba6d367c63192a52308ccf875e0fe4a6f3..dfc6821ed95a83c9ff6af68d1fc8ad217c67732c 100644 (file)
--- a/src/northbridge/amd/amdht/AsPsDefs.h
+++ b/src/northbridge/amd/amdht/AsPsDefs.h
@@ -157,7 +157,10 @@
 #define CPTC1 0xd8                     /* Clock Power/Timing Control1 Register*/
 #define VSRAMP_SLAM_MASK 0xffffff88    /* MaskOff [VSRampTime]&[VSSlamTime] */
 #define VSRAMP_SLAM_VALUE 0x16         /* [VSRampTime]=001b&[VSSlamTime]=110b */
+#define VSRAMP_MASK 0xffffff8f         /* MaskOff [VSRampTime] */
+#define VSRAMP_VALUE 0x10              /* [VSRampTime]=001b */
 #define VS_RAMP_T 4                    /* VSRampTime bit position */
+#define VSSLAM_MASK 0xfffffff8         /* MaskOff [VSSlamTime] */
 #define PWR_PLN_SHIFT 28               /* PwrPlanes bit shift */
 #define PWR_PLN_ON 0x10000000          /* PwrPlanes bit ON */
 #define PWR_PLN_OFF 0x0efffffff        /* PwrPlanes bit OFF */