#define PS_NB_VID_SHFT 25 /* P-state bit shift for NbVid */
#define PS_BOTH_VID_OFF 0x01ff01ff /* Mask NbVid & CpuVid */
#define PS_CPU_NB_VID_SHFT 16 /* P-state bit shift from CpuVid to NbVid */
-#define PS_NB_VID_SHFT 25 /* P-state NBVID shift */
#define PS_DIS 0x7fffffff /* disable P-state reg */
#define PS_EN 0x80000000 /* enable P-state reg */
#define PS_CPU_FID_MASK 0x03f /* MSRC001_00[68:64][CpuFid]
#define STC_PS_LMT_MASK 0x8fffffff /* StcPstateLimit mask off */
#define CPTC0 0x0d4 /* Clock Power/Timing Control0 Register*/
-#define CPTC0_MASK 0x000c0fff /* Reset mask for this register */
+#define CPTC0_MASK 0x000cffff /* Reset mask for this register */
#define CPTC0_NBFID_MASK 0xffffffe0 /* NbFid mask off for this register */
#define CPTC0_NBFID_MON 0x1f /* NbFid mask on for this register */
#define NB_FID_EN 0x20 /* NbFidEn bit ON */
#define TSC_MSR 0x10
#define CUR_PSTATE_MSR 0xc0010063
+#define TSC_FREQ_SEL_SHIFT 24
+
+#define TSC_FREQ_SEL_MASK (1 << TSC_FREQ_SEL_SHIFT)
#define WAIT_PSTATE_TIMEOUT 80000000 /* 0.1 s , unit : 1.25 ns */