*/
-static void print_raminit(const char *strval, u32 val)
-{
- printk_debug("%s%08x\n", strval, val);
-}
-
-
-#define RAMINIT_DEBUG 1
-
-
+#if (CONFIG_DIMM_SUPPORT & 0x000F)!=0x0005 /* not needed for AMD_FAM10_DDR3 */
static void print_tx(const char *strval, u32 val)
{
-#if RAMINIT_DEBUG == 1
- print_raminit(strval, val);
+#if CONFIG_DEBUG_RAM_SETUP
+ printk(BIOS_DEBUG, "%s%08x\n", strval, val);
#endif
}
-
+#endif
static void print_t(const char *strval)
{
-#if RAMINIT_DEBUG == 1
- print_debug(strval);
+#if CONFIG_DEBUG_RAM_SETUP
+ printk(BIOS_DEBUG, "%s", strval);
#endif
}
+
+#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
+#include "amdfam10.h"
+#include "../amdmct/wrappers/mcti.h"
+#include "../amdmct/amddefs.h"
+#include "../amdmct/mct_ddr3/mwlc_d.h"
+#include "../amdmct/mct_ddr3/mct_d.h"
+#include "../amdmct/mct_ddr3/mct_d_gcc.h"
+
+#include "../amdmct/wrappers/mcti_d.c"
+#include "../amdmct/mct_ddr3/mct_d.c"
+
+#include "../amdmct/mct_ddr3/mctmtr_d.c"
+#include "../amdmct/mct_ddr3/mctcsi_d.c"
+#include "../amdmct/mct_ddr3/mctecc_d.c"
+#include "../amdmct/mct_ddr3/mctdqs_d.c"
+#include "../amdmct/mct_ddr3/mctsrc.c"
+#include "../amdmct/mct_ddr3/mctsdi.c"
+#include "../amdmct/mct_ddr3/mctproc.c"
+#include "../amdmct/mct_ddr3/mctprob.c"
+#include "../amdmct/mct_ddr3/mcthwl.c"
+#include "../amdmct/mct_ddr3/mctwl.c"
+#include "../amdmct/mct_ddr3/mport_d.c"
+#include "../amdmct/mct_ddr3/mutilc_d.c"
+#include "../amdmct/mct_ddr3/modtrdim.c"
+#include "../amdmct/mct_ddr3/mhwlc_d.c"
+#include "../amdmct/mct_ddr3/mctrci.c"
+#include "../amdmct/mct_ddr3/mctsrc1p.c"
+#include "../amdmct/mct_ddr3/mcttmrl.c"
+#include "../amdmct/mct_ddr3/mcthdi.c"
+#include "../amdmct/mct_ddr3/mctndi_d.c"
+#include "../amdmct/mct_ddr3/mctchi_d.c"
+#include "../amdmct/mct_ddr3/modtrd.c"
+
+#if CONFIG_CPU_SOCKET_TYPE == 0x10
+//TODO: S1G1?
+#elif CONFIG_CPU_SOCKET_TYPE == 0x11
+//AM3
+#include "../amdmct/mct_ddr3/mctardk5.c"
+#elif CONFIG_CPU_SOCKET_TYPE == 0x12
+//F (1207), Fr2, G (1207)
+#include "../amdmct/mct_ddr3/mctardk6.c"
+#elif CONFIG_CPU_SOCKET_TYPE == 0x13
+//ASB2
+#include "../amdmct/mct_ddr3/mctardk5.c"
+//C32
+#elif CONFIG_CPU_SOCKET_TYPE == 0x14
+#include "../amdmct/mct_ddr3/mctardk5.c"
+#endif
+
+#else /* DDR2 */
+
#include "amdfam10.h"
#include "../amdmct/wrappers/mcti.h"
#include "../amdmct/amddefs.h"
#include "../amdmct/mct/mctndi_d.c"
#include "../amdmct/mct/mctchi_d.c"
-#if SYSTEM_TYPE == SERVER
+#if CONFIG_CPU_SOCKET_TYPE == 0x10
//L1
#include "../amdmct/mct/mctardk3.c"
-#elif SYSTEM_TYPE == DESKTOP
+#elif CONFIG_CPU_SOCKET_TYPE == 0x11
//AM2
#include "../amdmct/mct/mctardk4.c"
//#elif SYSTEM_TYPE == MOBILE
//#include "../amdmct/mct/mctardk5.c"
#endif
-#include "../amdmct/mct/mct_fd.c"
+#endif /* DDR2 */
int mctRead_SPD(u32 smaddr, u32 reg)
{
void mctSMBhub_Init(u32 node)
{
- struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+ struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
struct mem_controller *ctrl = &( sysinfo->ctrl[node] );
activate_spd_rom(ctrl);
}
void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node)
{
int j;
- struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+ struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
struct mem_controller *ctrl = &( sysinfo->ctrl[node] );
for(j=0;j<DIMM_SOCKETS;j++) {
u32 mctGetLogicalCPUID(u32 Node)
{
+ /* FIXME: Move this to a more generic place. Maybe to the CPU code */
+ /* Converts the CPUID to a logical ID MASK that is used to check
+ CPU version support versions */
u32 dev;
u32 val, valx;
u32 family, model, stepping;
u32 ret;
- dev = PA_NBMISC(Node);
- val = Get_NB32(dev, 0xfc);
- print_debug("Family_Model:"); print_debug_hex32(val); print_debug("\n");
- family = ((val >> 8) & 0x0f) + ((val>>20) & 0xff);
- model = ((val>>4) & 0x0f) | ((val>>(16-4)) & 0xf0);
- stepping = val & 0xff;
- print_debug("Family:"); print_debug_hex8(family); print_debug("\t");
- print_debug("Model:"); print_debug_hex8(model); print_debug("\t");
- print_debug("Stepping:"); print_debug_hex8(stepping); print_debug("\n");
+ if (Node == 0xFF) { /* current node */
+ val = cpuid_eax(0x80000001);
+ } else {
+ dev = PA_NBMISC(Node);
+ val = Get_NB32(dev, 0xfc);
+ }
+
+ family = ((val >> 8) & 0x0f) + ((val >> 20) & 0xff);
+ model = ((val >> 4) & 0x0f) | ((val >> (16-4)) & 0xf0);
+ stepping = val & 0x0f;
- valx = (family<<12) | (model<<4) | (stepping);
- print_debug("converted:"); print_debug_hex32(valx); print_debug("\n");
+ valx = (family << 12) | (model << 4) | (stepping);
switch (valx) {
case 0x10000:
case 0x10002:
ret = AMD_DR_A2;
break;
+ case 0x10020:
+ ret = AMD_DR_B0;
+ break;
+ case 0x10021:
+ ret = AMD_DR_B1;
+ break;
+ case 0x10022:
+ ret = AMD_DR_B2;
+ break;
+ case 0x10023:
+ ret = AMD_DR_B3;
+ break;
+ case 0x10042:
+ ret = AMD_RB_C2;
+ break;
+ case 0x10043:
+ ret = AMD_RB_C3;
+ break;
+ case 0x10062:
+ ret = AMD_DA_C2;
+ break;
+ case 0x10063:
+ ret = AMD_DA_C3;
+ break;
+ case 0x10080:
+ ret = AMD_HY_D0;
+ break;
+ case 0x10081:
+ ret = AMD_HY_D1;
+ break;
+ case 0x100a0:
+ ret = AMD_PH_E0;
+ break;
default:
+ /* FIXME: mabe we should die() here. */
+ print_err("FIXME! CPU Version unknown or not supported! \n");
ret = 0;
}
return ret;
}
+static u8 mctGetProcessorPackageType(void) {
+ /* FIXME: I guess this belongs wherever mctGetLogicalCPUID ends up ? */
+ u32 BrandId = cpuid_ebx(0x80000001);
+ return (u8)((BrandId >> 28) & 0x0F);
+}
-void raminit_amdmct(struct sys_info *sysinfo)
+static void raminit_amdmct(struct sys_info *sysinfo)
{
struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat);
struct DCTStatStruc *pDCTstatA = sysinfo->DCTstatA;
projects / coreboot.git / blobdiff