Revert "m5a99x-evo: ugly quirks, but WOOT: ohai seabios :-)"

[coreboot.git] / src / northbridge / amd / amdfam10 / northbridge.c

diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index d317b5114832ad8ff240d1248230e27868311d63..018b6c83b0d8e81dc3be08340885918f266e1b5b 100644 (file)
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -47,6 +47,11 @@
 #endif
 
 #include <cpu/amd/amdfam10_sysconf.h>
+#if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800
+#include <sb_cimx.h>
+#elif CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
+#include <SbEarly.h>
+#endif
 
 struct amdfam10_sysconf_t sysconf;
 
@@ -124,7 +129,7 @@ static u32 amdfam10_nodeid(device_t dev)
 #endif
 }
 
-#include "amdfam10_conf.c"
+#include "conf.c"
 
 static void set_vga_enable_reg(u32 nodeid, u32 linkn)
 {
@@ -841,8 +846,7 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id)
 #endif
 
 #if CONFIG_WRITE_HIGH_TABLES==1
-#define HIGH_TABLES_SIZE 64    // maximum size of high tables in KB
-extern uint64_t high_tables_base, high_tables_size;
+#include <cbmem.h>
 #endif
 
 #if CONFIG_GFXUMA == 1
@@ -1033,13 +1037,13 @@ static void amdfam10_domain_set_resources(device_t dev)
                                        if (high_tables_base==0) {
                                        /* Leave some space for ACPI, PIRQ and MP tables */
 #if CONFIG_GFXUMA == 1
-                                               high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
+                                               high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
 #else
-                                               high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
+                                               high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
 #endif
-                                               high_tables_size = HIGH_TABLES_SIZE * 1024;
-                                               printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE,
-                                                            high_tables_base);
+                                               high_tables_size = HIGH_MEMORY_SIZE;
+                                               printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
+                                                       HIGH_MEMORY_SIZE / 1024, high_tables_base);
                                        }
 #endif
                                }
@@ -1078,11 +1082,11 @@ static void amdfam10_domain_set_resources(device_t dev)
                if (high_tables_base==0) {
                /* Leave some space for ACPI, PIRQ and MP tables */
 #if CONFIG_GFXUMA == 1
-                       high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
+                       high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
 #else
-                       high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024;
+                       high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
 #endif
-                       high_tables_size = HIGH_TABLES_SIZE * 1024;
+                       high_tables_size = HIGH_MEMORY_SIZE;
                }
 #endif
        }
@@ -1446,6 +1450,10 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 static void cpu_bus_init(device_t dev)
 {
        initialize_cpus(dev->link_list);
+#if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 || CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
+       sb_After_Pci_Init();
+       sb_Mid_Post_Init();
+#endif
 }
 
 static void cpu_bus_noop(device_t dev)