remove trailing whitespace

[coreboot.git] / src / northbridge / amd / amdfam10 / amdfam10.h

diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index 029e5e7a6d2e63eb374bfab96b0f7aa7ca264884..99518065defbabd35801c78a39f765c97c644f98 100644 (file)
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -953,14 +953,24 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
 #define NonCoherent       (1 << 2)
 #define ConnectionPending (1 << 4)
 
+// Use the LAPIC timer count register to hold each core's init status
+//   Format: byte 0 - state
+//           byte 1 - fid_max
+//           byte 2 - nb_cof_vid_update
+//           byte 3 - apic id
 
-#include "amdfam10_nums.h"
+#define LAPIC_MSG_REG 0x380
+#define F10_APSTATE_STARTED 0x13  // start of AP execution
+#define F10_APSTATE_STOPPED 0x14  // allow AP to stop
+#define F10_APSTATE_RESET   0x01  // waiting for warm reset
 
-#ifdef __ROMCC__
+#include "nums.h"
+
+#ifdef __PRE_RAM__
 #if NODE_NUMS==64
-        #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CBB,(CDB+x),fn)):(PCI_DEV((CBB-1),(CDB+x-32),fn)))
+        #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
 #else
-        #define NODE_PCI(x, fn) PCI_DEV(CBB,(CDB+x),fn)
+        #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
 #endif
 #endif
 
@@ -996,7 +1006,11 @@ struct mem_info { // pernode
        u8 rsv[1];
 } __attribute__((packed));
 #else
-#include "../amdmct/mct/mct_d.h"
+ #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
+  #include "../amdmct/mct_ddr3/mct_d.h"
+ #else
+  #include "../amdmct/mct/mct_d.h"
+ #endif
 #endif
 
 struct link_pair_t {
@@ -1019,13 +1033,13 @@ struct nodes_info_t {
        u32 up_planes; // down planes will be [up_planes, planes)
 } __attribute__((packed));
 
-/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by linuxbios_car and linuxbios_ram stage. and linuxbios_ram may be running at 64bit later.*/
+/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and coreboot_ram stage. and coreboot_ram may be running at 64bit later.*/
 #if CONFIG_AMDMCT == 0
 
 //#define MEM_CS_COPY 1
 #define MEM_CS_COPY NODE_NUMS
 
-#if MEM_TRAIN_SEQ == 0
+#if CONFIG_MEM_TRAIN_SEQ == 0
        #define DQS_DELAY_COPY NODE_NUMS
 #else
 //     #define DQS_DELAY_COPY 1
@@ -1084,9 +1098,13 @@ struct sys_info {
 
 } __attribute__((packed));
 
+#ifndef __PRE_RAM__
+device_t get_node_pci(u32 nodeid, u32 fn);
+#endif
+
 #if CONFIG_AMDMCT == 0
 
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
 static void soft_reset(void);
 #endif
 static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
@@ -1131,10 +1149,10 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
        }
 
        for(i=0; i<sysinfo->nodes; i++) {
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
                print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n");
 #else
-               printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
+               printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
 #endif
                switch(sysinfo->mem_trained[i]) {
                case 0: //don't need train
@@ -1148,11 +1166,11 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
                }
        }
        if(needs_reset) {
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
                print_debug("mem trained failed\n");
                soft_reset();
 #else
-               printk_debug("mem trained failed\n");
+               printk(BIOS_DEBUG, "mem trained failed\n");
                hard_reset();
 #endif
        }
@@ -1161,4 +1179,27 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
 
 #endif
 
+#ifdef __PRE_RAM__
+void showallroutes(int level, device_t dev);
+
+void setup_resource_map_offset(const u32 *register_values, u32 max, u32
+               offset_pci_dev, u32 offset_io_base);
+
+void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32
+               offset_pci_dev, u32 offset_io_base);
+
+void setup_resource_map_x(const u32 *register_values, u32 max);
+
+/* reset_test.c */
+u32 cpu_init_detected(u8 nodeid);
+u32 bios_reset_detected(void);
+u32 cold_reset_detected(void);
+u32 other_reset_detected(void);
+u32 get_sblk(void);
+u8 get_sbbusn(u8 sblk);
+#endif
+
+#include "northbridge/amd/amdht/porting.h"
+BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, const u8 **List);
+
 #endif /* AMDFAM10_H */