* and acpi_is_wakeup_early_via_VX800() is part of Rudolf's S3 patch.
*/
-#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
+#define PAYLOAD_IS_SEABIOS 0
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
-#include "lib/ramtest.c"
+#include <console/console.h>
+#include <lib.h>
#include "northbridge/via/vx800/vx800.h"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include <string.h>
-#include "cpu/x86/lapic/boot_cpu.c"
-
/* This file contains the board-special SI value for raminit.c. */
#include "driving_clk_phase_data.c"
-
#include "northbridge/via/vx800/raminit.h"
#include "northbridge/via/vx800/raminit.c"
-#include "cpu/x86/car/copy_and_run.c"
#include "wakeup.h"
-
-#include "superio/winbond/w83697hf/w83697hf_early_serial.c"
+#include "superio/winbond/w83697hf/early_serial.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
/*
* This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list:
* http://www.coreboot.org/pipermail/coreboot/2008-January/028787.html.
*/
-void jason_tsc_count_car(void)
-{
-#if 0
- unsigned long long start;
- asm volatile ("rdtsc" : "=A" (start));
- start >>= 20;
- print_emerg("jason_tsc_count_car= ");
- print_emerg_hex32((unsigned long) start);
- print_emerg("\n");
-#endif
-}
-
-int acpi_is_wakeup_early_via_vx800(void)
+static int acpi_is_wakeup_early_via_vx800(void)
{
device_t dev;
u16 tmp, result;
return result;
}
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
/* All content of this function came from the cx700 port of coreboot. */
static void enable_mainboard_devices(void)
{
device_t dev;
- uint16_t values;
-
#if 0
/*
* Add and close this switch, since some line cause error, some
#if 0
dev = 0;
dev = pci_locate_device(PCI_ID(0x1106, PCI_DEVICE_ID_VIA_VX855_IDE), 0);
+
+ uint16_t values;
values = pci_read_config16(dev, 0xBA);
values &= ~0xffff;
values |= 0x5324;
*/
static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = {
/* VT3409 no PCI-E */
- 0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E, // Set Exxxxxxx as pcie mmio config range
- 0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B, // Support extended cfg address of pcie
- // 0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02, // APIC Interrupt((BT_INTR)) Control
+ { 0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E }, // Set Exxxxxxx as pcie mmio config range
+ { 0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B }, // Support extended cfg address of pcie
+ // { 0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02 }, // APIC Interrupt((BT_INTR)) Control
// Set ROMSIP value by software
/*
- 0x00, 0xFF, NB_HOST_REG(0x70), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pullup Driving = 3
- 0x00, 0xFF, NB_HOST_REG(0x71), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pulldown Driving = 3
- 0x00, 0xFF, NB_HOST_REG(0x72), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pullup Driving = 3
- 0x00, 0xFF, NB_HOST_REG(0x73), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pulldown Driving = 3
- 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0x21, // Memory I/F timing ctrl
- 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0xE1, // Memory I/F timing ctrl
- 0x00, 0xFF, NB_HOST_REG(0x75), 0xFF, 0x18, // AGTL+ I/O Circuit
- 0x00, 0xFF, NB_HOST_REG(0x76), 0xFB, 0x0C, // AGTL+ Compensation Status
- 0x00, 0xFF, NB_HOST_REG(0x78), 0xFF, 0x33, // 2X AGTL+ Auto Compensation Offset
- 0x00, 0xFF, NB_HOST_REG(0x79), 0xFF, 0x33, // 4X AGTL+ Auto Compensation Offset
- 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x72, // AGTL Compensation Status
- 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x77, // AGTL Compensation Status
- 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x44, // Input Host Address / Host Strobe Delay Control for HA Group
- 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x22, // Input Host Address / Host Strobe Delay Control for HA Group
- 0x00, 0xFF, NB_HOST_REG(0x7C), 0xFF, 0x00, // Output Delay Control of PAD for HA Group
- 0x00, 0xFF, NB_HOST_REG(0x7D), 0xFF, 0xAA, // Host Address / Address Clock Output Delay Control (Only for P4 Bus)
- 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
- 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
- 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
- 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
- 0x00, 0xFF, NB_HOST_REG(0x80), 0x3F, 0x44, // Host Data Receiving Strobe Delay Ctrl 1
- 0x00, 0xFF, NB_HOST_REG(0x81), 0xFF, 0x44, // Host Data Receiving Strobe Delay Ctrl 2
- 0x00, 0xFF, NB_HOST_REG(0x82), 0xFF, 0x00, // Output Delay of PAD for HDSTB
- 0x00, 0xFF, NB_HOST_REG(0x83), 0xFF, 0x00, // Output Delay of PAD for HD
- 0x00, 0xFF, NB_HOST_REG(0x84), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 0)
- 0x00, 0xFF, NB_HOST_REG(0x85), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 1)
- 0x00, 0xFF, NB_HOST_REG(0x86), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 2)
- 0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 3)
+ { 0x00, 0xFF, NB_HOST_REG(0x70), 0x77, 0x33 }, // 2x Host Adr Strobe/Pad Pullup Driving = 3
+ { 0x00, 0xFF, NB_HOST_REG(0x71), 0x77, 0x33 }, // 2x Host Adr Strobe/Pad Pulldown Driving = 3
+ { 0x00, 0xFF, NB_HOST_REG(0x72), 0x77, 0x33 }, // 4x Host Dat Strobe/Pad Pullup Driving = 3
+ { 0x00, 0xFF, NB_HOST_REG(0x73), 0x77, 0x33 }, // 4x Host Dat Strobe/Pad Pulldown Driving = 3
+ { 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0x21 }, // Memory I/F timing ctrl
+ { 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0xE1 }, // Memory I/F timing ctrl
+ { 0x00, 0xFF, NB_HOST_REG(0x75), 0xFF, 0x18 }, // AGTL+ I/O Circuit
+ { 0x00, 0xFF, NB_HOST_REG(0x76), 0xFB, 0x0C }, // AGTL+ Compensation Status
+ { 0x00, 0xFF, NB_HOST_REG(0x78), 0xFF, 0x33 }, // 2X AGTL+ Auto Compensation Offset
+ { 0x00, 0xFF, NB_HOST_REG(0x79), 0xFF, 0x33 }, // 4X AGTL+ Auto Compensation Offset
+ { 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x72 }, // AGTL Compensation Status
+ { 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x77 }, // AGTL Compensation Status
+ { 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x44 }, // Input Host Address / Host Strobe Delay Control for HA Group
+ { 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x22 }, // Input Host Address / Host Strobe Delay Control for HA Group
+ { 0x00, 0xFF, NB_HOST_REG(0x7C), 0xFF, 0x00 }, // Output Delay Control of PAD for HA Group
+ { 0x00, 0xFF, NB_HOST_REG(0x7D), 0xFF, 0xAA }, // Host Address / Address Clock Output Delay Control (Only for P4 Bus)
+ { 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x10 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
+ { 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x40 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
+ { 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x10 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
+ { 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x40 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
+ { 0x00, 0xFF, NB_HOST_REG(0x80), 0x3F, 0x44 }, // Host Data Receiving Strobe Delay Ctrl 1
+ { 0x00, 0xFF, NB_HOST_REG(0x81), 0xFF, 0x44 }, // Host Data Receiving Strobe Delay Ctrl 2
+ { 0x00, 0xFF, NB_HOST_REG(0x82), 0xFF, 0x00 }, // Output Delay of PAD for HDSTB
+ { 0x00, 0xFF, NB_HOST_REG(0x83), 0xFF, 0x00 }, // Output Delay of PAD for HD
+ { 0x00, 0xFF, NB_HOST_REG(0x84), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 0)
+ { 0x00, 0xFF, NB_HOST_REG(0x85), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 1)
+ { 0x00, 0xFF, NB_HOST_REG(0x86), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 2)
+ { 0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 3)
*/
// CPU Host Bus Control
- 0x00, 0xFF, NB_HOST_REG(0x50), 0x1F, 0x08, // Request phase ctrl: Dynamic Defer Snoop Stall Count = 8
- // 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW
- 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7C, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW
- 0x00, 0xFF, NB_HOST_REG(0x52), 0xCB, 0xCB, // CPU I/F Ctrl-2: Enable all for performance
- // 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK
- 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x44, // Arbitration: Host/Master Occupancy timer = 4*4 HCLK
- 0x00, 0xFF, NB_HOST_REG(0x54), 0x1E, 0x1C, // Misc Ctrl: Enable 8QW burst Mem Access
- // 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06, // Miscellaneous Control 2
- 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x04, // Miscellaneous Control 2
- 0x00, 0xFF, NB_HOST_REG(0x56), 0xF7, 0x63, // Write Policy 1
- // 0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL
- // 0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00, // CPU Miscellaneous Control 2
- 0x00, 0xFF, NB_HOST_REG(0x5D), 0xFF, 0xA2, // Write Policy
- 0x00, 0xFF, NB_HOST_REG(0x5E), 0xFF, 0x88, // Bandwidth Timer
- 0x00, 0xFF, NB_HOST_REG(0x5F), 0x46, 0x46, // CPU Misc Ctrl
- // 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B, // CPU Miscellaneous Control 3
- // 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B, // CPU Miscellaneous Control 2
- 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0A, // CPU Miscellaneous Control 2
- 0x00, 0xFF, NB_HOST_REG(0x98), 0xC1, 0x41, // CPU Miscellaneous Control 3
- 0x00, 0xFF, NB_HOST_REG(0x99), 0x0E, 0x06, // CPU Miscellaneous Control 4
+ { 0x00, 0xFF, NB_HOST_REG(0x50), 0x1F, 0x08 }, // Request phase ctrl: Dynamic Defer Snoop Stall Count = 8
+ // { 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F }, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW
+ { 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7C }, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW
+ { 0x00, 0xFF, NB_HOST_REG(0x52), 0xCB, 0xCB }, // CPU I/F Ctrl-2: Enable all for performance
+ // { 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88 }, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK
+ { 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x44 }, // Arbitration: Host/Master Occupancy timer = 4*4 HCLK
+ { 0x00, 0xFF, NB_HOST_REG(0x54), 0x1E, 0x1C }, // Misc Ctrl: Enable 8QW burst Mem Access
+ // { 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06 }, // Miscellaneous Control 2
+ { 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x04 }, // Miscellaneous Control 2
+ { 0x00, 0xFF, NB_HOST_REG(0x56), 0xF7, 0x63 }, // Write Policy 1
+ // { 0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01 }, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL
+ // { 0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00 }, // CPU Miscellaneous Control 2
+ { 0x00, 0xFF, NB_HOST_REG(0x5D), 0xFF, 0xA2 }, // Write Policy
+ { 0x00, 0xFF, NB_HOST_REG(0x5E), 0xFF, 0x88 }, // Bandwidth Timer
+ { 0x00, 0xFF, NB_HOST_REG(0x5F), 0x46, 0x46 }, // CPU Misc Ctrl
+ // { 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B }, // CPU Miscellaneous Control 3
+ // { 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B }, // CPU Miscellaneous Control 2
+ { 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0A }, // CPU Miscellaneous Control 2
+ { 0x00, 0xFF, NB_HOST_REG(0x98), 0xC1, 0x41 }, // CPU Miscellaneous Control 3
+ { 0x00, 0xFF, NB_HOST_REG(0x99), 0x0E, 0x06 }, // CPU Miscellaneous Control 4
// Set APIC and SMRAM
- 0x00, 0xFF, NB_HOST_REG(0x97), 0xFF, 0x00, // APIC Related Control
- 0x00, 0xFF, NB_DRAMC_REG(0x86), 0xD6, 0x29, // SMM and APIC Decoding: enable APIC, MSI and SMRAM A-Seg
- 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // End of the table
+ { 0x00, 0xFF, NB_HOST_REG(0x97), 0xFF, 0x00 }, // APIC Related Control
+ { 0x00, 0xFF, NB_DRAMC_REG(0x86), 0xD6, 0x29 }, // SMM and APIC Decoding: enable APIC, MSI and SMRAM A-Seg
+ { 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } // End of the table
};
#define USE_VCP 1 /* 0 means "use DVP". */
#define gCom1Base 0x3f8
#define gCom2Base 0x2f8
-void EmbedComInit(void)
+#if 0
+static void EmbedComInit(void)
{
u8 ByteVal;
u16 ComBase;
/* SOutput("Embedded COM output\n"); */
/* while(1); */
}
+#endif
/* cache_as_ram.inc jumps to here. */
-void stage1_main(unsigned long bist)
+void main(unsigned long bist)
{
- unsigned cpu_reset = 0;
u16 boot_mode;
u8 rambits, Data8, Data;
device_t device;
*/
pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01);
/* EmbedComInit(); */
- w83697hf_set_clksel_48(SERIAL_DEV);
+ w83697hf_set_clksel_48(DUMMY_DEV);
w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
/* enable_vx800_serial(); */
* g) Rx73h = 32h
*/
- jason_tsc_count_car();
-
pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBA,
PCI_DEVICE_ID_VIA_VX855_IDE);
pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBE,
/*
* There are two function definitions of console_init(), while the
- * src/arch/i386/lib is the right one.
+ * src/arch/x86/lib is the right one.
*/
console_init();
* written, then this must be a CPU restart (result of OS reboot cmd),
* so we need a real "cold boot".
*/
- jason_tsc_count_car();
if ((boot_mode != 3)
&& (pci_read_config8(PCI_DEV(0, 0, 3), 0x80) != 0)) {
outb(6, 0xcf9);
/* x86 cold boot I/O cmd. */
/* These 2 lines are the same with epia-cn port. */
enable_smbus();
- jason_tsc_count_car();
/* This fix does help vx800!, but vx855 doesn't need this. */
/* smbus_fixup(&ctrl); */
- if (bist == 0) {
- /*
- * CAR needs MTRR until memory is ok, so disable this
- * early_mtrr_init() call.
- */
-#if 0
- print_debug("doing early_mtrr\n");
- early_mtrr_init();
-#endif
- }
-
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
/* This line is the same with cx700 port. */
enable_shadow_ram();
- jason_tsc_count_car();
-
/*
* For coreboot most time of S3 resume is the same as normal boot,
* so some memory area under 1M become dirty, so before this happen,
- * I need to backup the content of mem to top-mem.
+ * I need to backup the content of mem to top-mem.
*
* I will reserve the 1M top-men in LBIO table in coreboot_table.c
* and recovery the content of 1M-mem in wakeup.c.
);
#endif
- /*
+ /*
* WAKE_MEM_INFO is inited in get_set_top_available_mem()
* in tables.c these two memcpy() not not be enabled if set
* the MTRR around this two lines.
);
#endif
}
-
-#endif
-
-/*
- * The following code is copied from tyan\s2735\romstage.c.
- * Only the code around CLEAR_FIRST_1M_RAM is changed. Removed all the code
- * around CLEAR_FIRST_1M_RAM and #include "cpu/x86/car/cache_as_ram_post.c".
- * The CLEAR_FIRST_1M_RAM seems to make cpu/x86/car/cache_as_ram_post.c stop
- * at somewhere, and cpu/x86/car/cache_as_ram_post.c do not cache my
- * $CONFIG_XIP_ROM_BASE+SIZE area.
- *
- * Use #include "cpu/via/car/cache_as_ram_post.c". This version post.c have
- * some diff with x86-version.
- */
-#if 1
- {
- /*
- * Check value of esp to verify if we have enough ROM for
- * stack in Cache as RAM.
- */
- unsigned v_esp;
- __asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp));
-#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "v_esp=%08x\n", v_esp);
-#else
- print_debug("v_esp=");
- print_debug_hex32(v_esp);
- print_debug("\n");
-#endif
- }
-#endif
-
-#if 1
-cpu_reset_x:
-
- /* It seems that cpu_reset is not used before this, so I just reset
- * it, (this is because the s3 resume, setting in MTRR and copy data
- * may destroy stack.
- */
- cpu_reset = 0;
-
-#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "cpu_reset = %08x\n", cpu_reset);
-#else
- print_debug("cpu_reset = ");
- print_debug_hex32(cpu_reset);
- print_debug("\n");
-#endif
-
- if (cpu_reset == 0)
- print_debug("Clearing initial memory region: ");
- print_debug("No cache as ram now - ");
-
- /* Store cpu_reset to ebx. */
- __asm__ volatile ("movl %0, %%ebx\n\t"::"a" (cpu_reset));
-
- /*
- * Cancel these lines, CLEAR_FIRST_1M_RAM cause the
- * cpu/x86/car/cache_as_ram_post.c stop at somewhere.
- */
-#if 0
- if (cpu_reset == 0) {
-#define CLEAR_FIRST_1M_RAM 1
-#include "cpu/via/car/cache_as_ram_post.c"
- } else {
-#undef CLEAR_FIRST_1M_RAM
-#include "cpu/via/car/cache_as_ram_post.c"
- }
#endif
-
-#include "cpu/via/car/cache_as_ram_post.c"
-/* #include "cpu/x86/car/cache_as_ram_post.c" */
- __asm__ volatile (
- /* Set new esp *//* before CONFIG_RAMBASE */
- "subl %0, %%ebp\n\t"
- "subl %0, %%esp\n\t"::
- "a" ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - CONFIG_RAMBASE)
- );
-
- {
- unsigned new_cpu_reset;
-
- /* Get back cpu_reset from ebx. */
- __asm__ volatile ("movl %%ebx, %0\n\t":"=a" (new_cpu_reset));
-
- /* We can't go back anymore, we lost old stack data in CAR. */
- if (new_cpu_reset == 0)
- print_debug("Use Ram as Stack now - done\n");
- else
- print_debug("Use Ram as Stack now - \n");
-
-#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "new_cpu_reset = %08x\n", new_cpu_reset);
-#else
- print_debug("new_cpu_reset = ");
- print_debug_hex32(new_cpu_reset);
- print_debug("\n");
-#endif
-
- jason_tsc_count_car();
- /* Copy and execute coreboot_ram. */
- copy_and_run(new_cpu_reset);
- /* We will not return. */
- }
-#endif
-
- print_debug("should not be here -\n");
}
-
projects / coreboot.git / blobdiff