Build fix.

[coreboot.git] / src / mainboard / tyan / s2912_fam10 / romstage.c

diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 5963d18d672dbcce9407aa8b9406194664b732d8..a3ffff902e4c3f0b19135351a3e81f9e65e07793 100644 (file)
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -128,6 +128,7 @@ static const u8 spd_addr[] = {
        //second node
        RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
 #endif
+};
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {