remove trailing whitespace

[coreboot.git] / src / mainboard / supermicro / h8scm_fam10 / romstage.c

diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index da0ab06a1a110cc6ebbc22a5b65a08d14c35a6d7..70b3a0470d483dbb4d284dcbaf24baa3ce52c26b 100644 (file)
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -42,13 +42,13 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-#include "superio/nuvoton/wpcm450/early_init.c"
-#include <usbdebug.h>
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/sb700/early_setup.c"
-#include "southbridge/amd/sr5650/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
+#include "southbridge/amd/sr5650/sr5650.h"
+#include "superio/nuvoton/wpcm450/wpcm450.h"
 #include "northbridge/amd/amdfam10/debug.c"
 
 static void activate_spd_rom(const struct mem_controller *ctrl)
@@ -57,7 +57,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl)
 
 static int spd_read_byte(u32 device, u32 address)
 {
-       return smbus_read_byte(device, address);
+       return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
@@ -102,7 +102,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                set_bsp_node_CHtExtNodeCfgEn();
                enumerate_ht_chain();
 
-               disable_pcie_bridge();
+               /* SR56x0 pcie bridges block pci_locate_device() before pcie training.
+                * disable all pcie bridges on SR56x0 to work around it
+                */
+               sr5650_disable_pcie_bridge();
                sb7xx_51xx_lpc_port80();
        }
 
@@ -123,14 +126,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        wpcm450_enable_dev(WPCM450_SP1, 0x164E, CONFIG_TTYS0_BASE);
 
        sb7xx_51xx_disable_wideio(0);
-       uart_init();
 
-#if CONFIG_USBDEBUG
-       sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-       early_usbdebug_init();
-#endif
        console_init();
-       printk(BIOS_DEBUG, "\n");
 
 //     dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 
@@ -187,7 +184,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        /* run _early_setup before soft-reset. */
        sr5650_early_setup();
-       disable_pcie_bridge();
        sb7xx_51xx_early_setup();
 
 #if CONFIG_SET_FIDVID