Simplify a few code chunks, fix whitespace and indentation.

[coreboot.git] / src / mainboard / supermicro / h8dmr_fam10 / romstage.c

diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 174a6cefcf871d2e178a575490fb0da5da8f860b..61551a718c247ecff0b8822fd349771156b79b6a 100644 (file)
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -51,10 +51,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-       /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
@@ -111,30 +108,22 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
                CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
-       u32 bsp_apicid = 0;
-       u32 val;
-       u32 wants_reset;
+       u32 bsp_apicid = 0, val, wants_reset;
        msr_t msr;
 
        if (!cpu_init_detectedx && boot_cpu()) {
                /* Nothing special needs to be done to find bus 0 */
                /* Allow the HT devices to be found */
-
                set_bsp_node_CHtExtNodeCfgEn();
                enumerate_ht_chain();
-
                sio_setup();
-
-               /* Setup the mcp55 */
                mcp55_enable_rom();
        }
 
        post_code(0x30);
 
-       if (bist == 0) {
+       if (bist == 0)
                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-       }
 
        post_code(0x32);