Use DIMM0 et al in lots more places instead of hardocding values.

[coreboot.git] / src / mainboard / supermicro / h8dme / romstage.c

diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index 86705fdfb64cad7dcce67054384b02281ef12530..4f32816ebb79764ecee12b6a2564fc39aa2c5654 100644 (file)
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -32,6 +32,7 @@
 
 #include <console/console.h>
 #include <lib.h>
+#include <spd.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 
@@ -188,15 +189,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  */
        static const uint16_t spd_addr[] = {
                // Node 0
-               RC0 | (0xa << 3) | 0, RC0 | (0xa << 3) | 2,
-                   RC0 | (0xa << 3) | 4, RC0 | (0xa << 3) | 6,
-               RC0 | (0xa << 3) | 1, RC0 | (0xa << 3) | 3,
-                   RC0 | (0xa << 3) | 5, RC0 | (0xa << 3) | 7,
+               RC0 | DIMM0, RC0 | DIMM2,
+               RC0 | DIMM4, RC0 | DIMM6,
+               RC0 | DIMM1, RC0 | DIMM3,
+               RC0 | DIMM5, RC0 | DIMM7,
                // Node 1
-               RC1 | (0xa << 3) | 0, RC1 | (0xa << 3) | 2,
-                   RC1 | (0xa << 3) | 4, RC1 | (0xa << 3) | 6,
-               RC1 | (0xa << 3) | 1, RC1 | (0xa << 3) | 3,
-                   RC1 | (0xa << 3) | 5, RC1 | (0xa << 3) | 7,
+               RC1 | DIMM0, RC1 | DIMM2,
+               RC1 | DIMM4, RC1 | DIMM6,
+               RC1 | DIMM1, RC1 | DIMM3,
+               RC1 | DIMM5, RC1 | DIMM7,
        };
 
        struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE