Use DIMM0 et al in lots more places instead of hardocding values.

[coreboot.git] / src / mainboard / sunw / ultra40 / romstage.c

diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c
index 32204b02386eb5dd931969d2d0ac66310e682e69..1f567402d22a08278db9454f6b4819dd6c6edd35 100644 (file)
--- a/src/mainboard/sunw/ultra40/romstage.c
+++ b/src/mainboard/sunw/ultra40/romstage.c
@@ -8,6 +8,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <lib.h>
+#include <spd.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
@@ -117,11 +118,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr [] = {
                        // Node 0
-                       (0xa<<3)|0, (0xa<<3)|2, 0, 0,
-                       (0xa<<3)|1, (0xa<<3)|3, 0, 0,
+                       DIMM0, DIMM2, 0, 0,
+                       DIMM1, DIMM3, 0, 0,
                        // Node 1
-                       (0xa<<3)|4, (0xa<<3)|6, 0, 0,
-                       (0xa<<3)|5, (0xa<<3)|7, 0, 0,
+                       DIMM4, DIMM6, 0, 0,
+                       DIMM5, DIMM7, 0, 0,
        };
 
         int needs_reset;