Use DIMM0 et al in lots more places instead of hardocding values.

[coreboot.git] / src / mainboard / nvidia / l1_2pvv / romstage.c

diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index 447d38d89030dc3c2f2437781ebd7a40a06cb1c9..ed8e33a6073f477d9d4ca41ef141a23f3f920ac3 100644 (file)
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -36,6 +36,7 @@
 #include <console/console.h>
 #include <usbdebug.h>
 #include <lib.h>
+#include <spd.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 
@@ -132,11 +133,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr [] = {
                        // Node 0
-                       (0xa<<3)|0, (0xa<<3)|2, 0, 0,
-                       (0xa<<3)|1, (0xa<<3)|3, 0, 0,
+                       DIMM0, DIMM2, 0, 0,
+                       DIMM1, DIMM3, 0, 0,
                        // Node 1
-                       (0xa<<3)|4, (0xa<<3)|6, 0, 0,
-                       (0xa<<3)|5, (0xa<<3)|7, 0, 0,
+                       DIMM4, DIMM6, 0, 0,
+                       DIMM5, DIMM7, 0, 0,
        };
 
        struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE