Simplify a few code chunks, fix whitespace and indentation.

[coreboot.git] / src / mainboard / newisys / khepri / romstage.c

diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c
index 11e1ecfe3ebf43bf0fffa11958e1cddbf4e42645..bd62cad9cc9c6411c18d687892c2c4601efdfe36 100644 (file)
--- a/src/mainboard/newisys/khepri/romstage.c
+++ b/src/mainboard/newisys/khepri/romstage.c
@@ -35,14 +35,13 @@
 static void memreset_setup(void)
 {
        if (is_cpu_pre_c0()) {
-               /* Set the memreset low */
-               outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
-               /* Ensure the BIOS has control of the memory lines */
-               outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
-       }
-       else {
-               /* Ensure the CPU has controll of the memory lines */
-               outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
+               /* Set the memreset low. */
+               outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
+               /* Ensure the BIOS has control of the memory lines. */
+               outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
+       } else {
+               /* Ensure the CPU has control of the memory lines. */
+               outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
        }
 }
 
@@ -50,16 +49,13 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
 {
        if (is_cpu_pre_c0()) {
                udelay(800);
-               /* Set memreset_high */
-               outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
+               /* Set memreset high. */
+               outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
                udelay(90);
        }
 }
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-       /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
@@ -69,7 +65,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
-#include "resourcemap.c" /* newisys khepri does not want the default */
+#include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
@@ -79,35 +75,27 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr [] = {
-                       DIMM0, DIMM2, 0, 0,
-                       DIMM1, DIMM3, 0, 0,
+               DIMM0, DIMM2, 0, 0,
+               DIMM1, DIMM3, 0, 0,
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
-                       DIMM4, DIMM6, 0, 0,
-                       DIMM5, DIMM7, 0, 0,
+               DIMM4, DIMM6, 0, 0,
+               DIMM5, DIMM7, 0, 0,
 #endif
        };
 
         int needs_reset;
-        unsigned bsp_apicid = 0;
-
+        unsigned bsp_apicid = 0, nodes;
         struct mem_controller ctrl[8];
-        unsigned nodes;
 
         if (!cpu_init_detectedx && boot_cpu()) {
                /* Nothing special needs to be done to find bus 0 */
                /* Allow the HT devices to be found */
-
                enumerate_ht_chain();
-
-               /* Setup the amd8111 */
                amd8111_enable_rom();
         }
 
-        if (bist == 0) {
+        if (bist == 0)
                 bsp_apicid = init_cpus(cpu_init_detectedx);
-        }
-
-//     post_code(0x32);
 
        w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
         uart_init();