After this has been brought up many times before, rename src/arch/i386 to

[coreboot.git] / src / mainboard / intel / truxton / romstage.c

diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c
index 0559ecb4f48715143f54aa6e66fc3d49ce525e00..af7d1bf2094db11dc348c056b587af08a2fcdad7 100644 (file)
--- a/src/mainboard/intel/truxton/romstage.c
+++ b/src/mainboard/intel/truxton/romstage.c
@@ -15,11 +15,8 @@
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- *
  */
 
-#define ASSEMBLY 1
-
 #include <stdint.h>
 #include <stdlib.h>
 #include <device/pci_def.h>
@@ -28,30 +25,21 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
+#include <pc80/mc146818rtc.h>
 #include "pc80/udelay_io.c"
-#include "arch/i386/lib/console.c"
-#include "lib/ramtest.c"
-#include "southbridge/intel/i3100/i3100_early_smbus.c"
-#include "southbridge/intel/i3100/i3100_early_lpc.c"
+#include <console/console.h>
+#include "southbridge/intel/i3100/early_smbus.c"
+#include "southbridge/intel/i3100/early_lpc.c"
 #include "northbridge/intel/i3100/raminit_ep80579.h"
 #include "superio/intel/i3100/i3100.h"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
-#include "superio/intel/i3100/i3100_early_serial.c"
+#include "superio/intel/i3100/early_serial.c"
 #include "cpu/x86/bist.h"
-#include "spd.h"
-
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
+#include <spd.h>
 
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0)
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-       /* nothing to do */
-}
 static inline int spd_read_byte(u16 device, u8 address)
 {
        return smbus_read_byte(device, address);
@@ -60,8 +48,9 @@ static inline int spd_read_byte(u16 device, u8 address)
 #include "northbridge/intel/i3100/raminit_ep80579.c"
 #include "lib/generic_sdram.c"
 #include "../../intel/jarrell/debug.c"
+#include "arch/x86/lib/stages.c"
 
-/* #define TRUXTON_DEBUG */
+#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
 
 static void main(unsigned long bist)
 {
@@ -71,21 +60,22 @@ static void main(unsigned long bist)
                {
                        .node_id = 0,
                        .f0 = PCI_DEV(0, 0x00, 0),
-                       .channel0 = { (0xa<<3)|2, (0xa<<3)|3 },
+                       .channel0 = { DIMM2, DIMM3 },
                }
        };
 
        if (bist == 0) {
                /* Skip this if there was a built in self test failure */
                early_mtrr_init();
-               if (memory_initialized()) {
-                       asm volatile ("jmp __cpu_reset");
-               }
+               if (memory_initialized())
+                       skip_romstage();
        }
 
        /* Set up the console */
        i3100_enable_superio();
-       i3100_enable_serial(I3100_SUPERIO_CONFIG_PORT, I3100_SP1, CONFIG_TTYS0_BASE);
+       i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+       i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);
+
        uart_init();
        console_init();
 
@@ -107,9 +97,4 @@ static void main(unsigned long bist)
 #ifdef TRUXTON_DEBUG
        dump_bar14(PCI_DEV(0, 0x00, 0));
 #endif
-
-#ifdef TRUXTON_DEBUG
-       ram_fill(0x00000000, 0x02000000);
-       ram_verify(0x00000000, 0x02000000);
-#endif
 }