Restructure i3100 Super I/O driver to match the rest of the codebase.

[coreboot.git] / src / mainboard / intel / mtarvon / romstage.c

diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c
index 89fb5439efa4158ef168615c4050c856480c9229..f36e4a4e681568957528ebc3bdd7b8883ca53382 100644 (file)
--- a/src/mainboard/intel/mtarvon/romstage.c
+++ b/src/mainboard/intel/mtarvon/romstage.c
@@ -40,6 +40,8 @@
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0)
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
+#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
+
 static inline int spd_read_byte(u16 device, u8 address)
 {
        return smbus_read_byte(device, address);
@@ -75,9 +77,12 @@ void main(unsigned long bist)
                }
 #endif
        }
+
        /* Set up the console */
        i3100_enable_superio();
-       i3100_enable_serial(0x4e, I3100_SP1, CONFIG_TTYS0_BASE);
+       i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+       i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);
+
        uart_init();
        console_init();