Use DIMM0 et al in lots more places instead of hardocding values.

[coreboot.git] / src / mainboard / intel / mtarvon / romstage.c

diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c
index f36e4a4e681568957528ebc3bdd7b8883ca53382..5d34058a843e765f885bdab33ae16c6283dfb80e 100644 (file)
--- a/src/mainboard/intel/mtarvon/romstage.c
+++ b/src/mainboard/intel/mtarvon/romstage.c
@@ -36,6 +36,7 @@
 #include "superio/intel/i3100/i3100_early_serial.c"
 #include "northbridge/intel/i3100/memory_initialized.c"
 #include "cpu/x86/bist.h"
+#include <spd.h>
 
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0)
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
@@ -64,8 +65,8 @@ void main(unsigned long bist)
                        .f1 = PCI_DEV(0, 0x00, 1),
                        .f2 = PCI_DEV(0, 0x00, 2),
                        .f3 = PCI_DEV(0, 0x00, 3),
-                       .channel0 = { (0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0 },
-                       .channel1 = { (0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4 },
+                       .channel0 = { DIMM3, DIMM2, DIMM1, DIMM0 },
+                       .channel1 = { DIMM7, DIMM6, DIMM5, DIMM4 },
                }
        };