After this has been brought up many times before, rename src/arch/i386 to

[coreboot.git] / src / mainboard / intel / jarrell / romstage.c

diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c
index 530c22ae2493984b8531451ead5e69b16cd406da..b8167758616007cd1739fdeef04f83779114388c 100644 (file)
--- a/src/mainboard/intel/jarrell/romstage.c
+++ b/src/mainboard/intel/jarrell/romstage.c
@@ -6,8 +6,7 @@
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
-#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
+#include "southbridge/intel/i82801ex/early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/nsc/pc87427/pc87427.h"
 #include "cpu/x86/lapic/boot_cpu.c"
@@ -16,9 +15,10 @@
 #include "reset.c"
 #include "power_reset_check.c"
 #include "jarrell_fixups.c"
-#include "superio/nsc/pc87427/pc87427_early_init.c"
+#include "superio/nsc/pc87427/early_init.c"
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
+#include <spd.h>
 
 #define SIO_GPIO_BASE 0x680
 #define SIO_XBUS_BASE 0x4880
@@ -37,35 +37,25 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/intel/e7520/raminit.c"
 #include "lib/generic_sdram.c"
 #include "debug.c"
-#include "arch/i386/lib/stages.c"
+#include "arch/x86/lib/stages.c"
 
 static void main(unsigned long bist)
 {
-       /*
-        *
-        *
-        */
        static const struct mem_controller mch[] = {
                {
                        .node_id = 0,
-                       /*
-                       .f0 = PCI_DEV(0, 0x00, 0),
-                       .f1 = PCI_DEV(0, 0x00, 1),
-                       .f2 = PCI_DEV(0, 0x00, 2),
-                       .f3 = PCI_DEV(0, 0x00, 3),
-                       */
-                       .channel0 = { (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, 0 },
-                       .channel1 = { (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, 0 },
+                       .channel0 = { DIMM2, DIMM1, DIMM0, 0 },
+                       .channel1 = { DIMM6, DIMM5, DIMM4, 0 },
                }
        };
 
        if (bist == 0) {
                /* Skip this if there was a built in self test failure */
                early_mtrr_init();
-               if (memory_initialized()) {
+               if (memory_initialized())
                        skip_romstage();
-               }
        }
+
        /* Setup the console */
        pc87427_disable_dev(CONSOLE_SERIAL_DEV);
        pc87427_disable_dev(HIDDEN_SERIAL_DEV);
@@ -88,9 +78,8 @@ static void main(unsigned long bist)
        /* config LPC decode for flash memory access */
         device_t dev;
         dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
-        if (dev == PCI_DEV_INVALID) {
+        if (dev == PCI_DEV_INVALID)
                 die("Missing ich5?");
-        }
         pci_write_config32(dev, 0xe8, 0x00000000);
         pci_write_config8(dev, 0xf0, 0x00);
 
@@ -101,9 +90,8 @@ static void main(unsigned long bist)
 #if 0
 //     dump_spd_registers(&cpu[0]);
        int i;
-       for(i = 0; i < 1; i++) {
+       for(i = 0; i < 1; i++)
                dump_spd_registers();
-       }
 #endif
        disable_watchdogs();
        power_down_reset_check();
@@ -113,28 +101,7 @@ static void main(unsigned long bist)
        ich5_watchdog_on();
 #if 0
        dump_pci_devices();
-#endif
-#if 0
        dump_pci_device(PCI_DEV(0, 0x00, 0));
        dump_bar14(PCI_DEV(0, 0x00, 0));
 #endif
-
-#if 0 // temporarily disabled
-       /* Check the first 1M */
-//     ram_check(0x00000000, 0x000100000);
-//     ram_check(0x00000000, 0x000a0000);
-       ram_check(0x00100000, 0x01000000);
-       /* check the first 1M in the 3rd Gig */
-       ram_check(0x30100000, 0x31000000);
-#if 0
-       ram_check(0x00000000, 0x02000000);
-#endif
-
-#endif
-#if 0
-       while(1) {
-               hlt();
-       }
-#endif
 }
-