Restructure i3100 Super I/O driver to match the rest of the codebase.

[coreboot.git] / src / mainboard / intel / eagleheights / romstage.c

diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index 8ffe22c168a52869d5c8e531d83c65e6a15018b1..8e1d21236330d7eb50d3fd2a707a601b44736c3d 100644 (file)
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -91,6 +91,8 @@ static inline int spd_read_byte(u16 device, u8 address)
 #include "northbridge/intel/i3100/reset_test.c"
 #include "debug.c"
 
+#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
+
 static void early_config(void)
 {
        u32 gcs, rpc, fd;
@@ -157,7 +159,9 @@ void main(unsigned long bist)
 
        /* Setup the console */
        i3100_enable_superio();
-       i3100_enable_serial(0x4E, I3100_SP1, CONFIG_TTYS0_BASE);
+       i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+       i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);
+
        uart_init();
        console_init();