Simplify a few code chunks, fix whitespace and indentation.

[coreboot.git] / src / mainboard / intel / d945gclf / romstage.c

diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 8d155d1662a58263bb2c9cd7d3079e5790b6cbc3..8b79f2dc571de7f6a93a22a3a5dfe4c106189de0 100644 (file)
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -201,9 +201,8 @@ void main(unsigned long bist)
        u32 reg32;
        int boot_mode = 0;
 
-       if (bist == 0) {
+       if (bist == 0)
                enable_lapic();
-       }
 
        ich7_enable_lpc();
        early_superio_config_lpc47m15x();