Since some people disapprove of white space cleanups mixed in regular commits

[coreboot.git] / src / mainboard / ibm / e326 / resourcemap.c

diff --git a/src/mainboard/ibm/e326/resourcemap.c b/src/mainboard/ibm/e326/resourcemap.c
index a37496879b03b4ea321da820cf67bd7ebc2206b3..98fdcc0ec620908ad8b942475f7be1399b280cf9 100644 (file)
--- a/src/mainboard/ibm/e326/resourcemap.c
+++ b/src/mainboard/ibm/e326/resourcemap.c
@@ -134,7 +134,7 @@ static void setup_ibm_e326_resource_map(void)
         *         1 = base/limit registers i are read-only
         * [ 7: 4] Reserved
         * [31: 8] Memory-Mapped I/O Base Address i (39-16)
-        *         This field defines the upper address bits of a 40bit address 
+        *         This field defines the upper address bits of a 40bit address
         *         that defines the start of memory-mapped I/O region i
         */
 
@@ -143,8 +143,8 @@ static void setup_ibm_e326_resource_map(void)
        //PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0x0,
        // PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0x0,
 
-       PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0xfec010, 
-       PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0xfec003, 
+       PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0xfec010,
+       PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0xfec003,
        //PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0x0,
        //PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0x0,
 
@@ -153,19 +153,19 @@ static void setup_ibm_e326_resource_map(void)
        //PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0x0,
        //PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0x0,
 
-       PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0xfed010, 
+       PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0xfed010,
        PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0xfed003,
        //PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0x0,
        //PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0x0,
 
-       PCI_ADDR(0, 0x18, 1, 0x9c), 0x48, 0x0, 
-       PCI_ADDR(0, 0x18, 1, 0x98), 0xf0, 0x0, 
-       PCI_ADDR(0, 0x18, 1, 0x94), 0x48, 0x0, 
-       PCI_ADDR(0, 0x18, 1, 0x90), 0xf0, 0x0, 
-       PCI_ADDR(0, 0x18, 1, 0x8c), 0x48, 0x0, 
-       PCI_ADDR(0, 0x18, 1, 0x88), 0xf0, 0x0, 
-       PCI_ADDR(0, 0x18, 1, 0x84), 0x48, 0x0, 
-       PCI_ADDR(0, 0x18, 1, 0x80), 0xf0, 0x0, 
+       PCI_ADDR(0, 0x18, 1, 0x9c), 0x48, 0x0,
+       PCI_ADDR(0, 0x18, 1, 0x98), 0xf0, 0x0,
+       PCI_ADDR(0, 0x18, 1, 0x94), 0x48, 0x0,
+       PCI_ADDR(0, 0x18, 1, 0x90), 0xf0, 0x0,
+       PCI_ADDR(0, 0x18, 1, 0x8c), 0x48, 0x0,
+       PCI_ADDR(0, 0x18, 1, 0x88), 0xf0, 0x0,
+       PCI_ADDR(0, 0x18, 1, 0x84), 0x48, 0x0,
+       PCI_ADDR(0, 0x18, 1, 0x80), 0xf0, 0x0,
        /* PCI I/O Limit i Registers
         * F1:0xC4 i = 0
         * F1:0xCC i = 1
@@ -205,7 +205,7 @@ static void setup_ibm_e326_resource_map(void)
         * [ 3: 2] Reserved
         * [ 4: 4] VGA Enable
         *         0 = VGA matches Disabled
-        *         1 = matches all address < 64K and where A[9:0] is in the 
+        *         1 = matches all address < 64K and where A[9:0] is in the
         *             range 3B0-3BB or 3C0-3DF independen of the base & limit registers
         * [ 5: 5] ISA Enable
         *         0 = ISA matches Disabled
@@ -213,17 +213,17 @@ static void setup_ibm_e326_resource_map(void)
         *             from matching agains this base/limit pair
         * [11: 6] Reserved
         * [24:12] PCI I/O Base i
-        *         This field defines the start of PCI I/O region n 
+        *         This field defines the start of PCI I/O region n
         * [31:25] Reserved
         */
-       PCI_ADDR(0, 0x18, 1, 0xdc), 0xFE000FC8, 0x1fff010, 
-       PCI_ADDR(0, 0x18, 1, 0xd8), 0xFE000FCC, 0x33, 
-       PCI_ADDR(0, 0x18, 1, 0xd4), 0xFE000FC8, 0x0, 
-       PCI_ADDR(0, 0x18, 1, 0xd0), 0xFE000FCC, 0x0, 
-       PCI_ADDR(0, 0x18, 1, 0xcc), 0xFE000FC8, 0x0, 
-       PCI_ADDR(0, 0x18, 1, 0xc8), 0xFE000FCC, 0x0, 
-       PCI_ADDR(0, 0x18, 1, 0xc4), 0xFE000FC8, 0x0, 
-       PCI_ADDR(0, 0x18, 1, 0xc0), 0xFE000FCC, 0x0, 
+       PCI_ADDR(0, 0x18, 1, 0xdc), 0xFE000FC8, 0x1fff010,
+       PCI_ADDR(0, 0x18, 1, 0xd8), 0xFE000FCC, 0x33,
+       PCI_ADDR(0, 0x18, 1, 0xd4), 0xFE000FC8, 0x0,
+       PCI_ADDR(0, 0x18, 1, 0xd0), 0xFE000FCC, 0x0,
+       PCI_ADDR(0, 0x18, 1, 0xcc), 0xFE000FC8, 0x0,
+       PCI_ADDR(0, 0x18, 1, 0xc8), 0xFE000FCC, 0x0,
+       PCI_ADDR(0, 0x18, 1, 0xc4), 0xFE000FC8, 0x0,
+       PCI_ADDR(0, 0x18, 1, 0xc0), 0xFE000FCC, 0x0,
        /* Config Base and Limit i Registers
         * F1:0xE0 i = 0
         * F1:0xE4 i = 1
@@ -260,10 +260,10 @@ static void setup_ibm_e326_resource_map(void)
         * [31:24] Bus Number Limit i
         *         This field defines the highest bus number in configuration regin i
         */
-       PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000FC88, 0xff040103, 
-       PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000FC88, 0, 
-       PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000FC88, 0, 
-       PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0, 
+       PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000FC88, 0xff040103,
+       PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000FC88, 0,
+       PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000FC88, 0,
+       PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0,
         };
         int max;
         max = ARRAY_SIZE(register_values);