Simplify a few code chunks, fix whitespace and indentation.

[coreboot.git] / src / mainboard / gigabyte / ma78gm / romstage.c

diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 116229605e258d4f03d74292bdd769ca24512866..9a753b9201314e0072381d7d943504c8534ad9cf 100644 (file)
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -52,15 +52,11 @@ static int smbus_read_byte(u32 device, u32 address);
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
 static int spd_read_byte(u32 device, u32 address)
 {
-       int result;
-       result = smbus_read_byte(device, address);
-       return result;
+       return smbus_read_byte(device, address);
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
@@ -80,8 +76,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
        static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
-       u32 bsp_apicid = 0;
-       u32 val;
+       u32 bsp_apicid = 0, val;
        msr_t msr;
 
        if (!cpu_init_detectedx && boot_cpu()) {
@@ -90,7 +85,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                /* mov bsp to bus 0xff when > 8 nodes */
                set_bsp_node_CHtExtNodeCfgEn();
                enumerate_ht_chain();
-
                sb700_pci_port80();
        }
 
@@ -155,13 +149,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         */
        wait_all_core0_started();
 
- #if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS==1
        /* Core0 on each node is configured. Now setup any additional cores. */
        printk(BIOS_DEBUG, "start_other_cores()\n");
        start_other_cores();
        post_code(0x37);
        wait_all_other_cores_started(bsp_apicid);
- #endif
+#endif
 
        post_code(0x38);
 
@@ -169,7 +163,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        rs780_early_setup();
        sb700_early_setup();
 
- #if CONFIG_SET_FIDVID
+#if CONFIG_SET_FIDVID
        msr = rdmsr(0xc0010071);
        printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 
@@ -190,7 +184,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        /* show final fid and vid */
        msr=rdmsr(0xc0010071);
        printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
- #endif
+#endif
 
        rs780_htinit();