Since some people disapprove of white space cleanups mixed in regular commits

[coreboot.git] / src / mainboard / gigabyte / m57sli / romstage.c

diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index 1e3bee8845e722b3ac0532bccc9488912c00fb5a..3f2f5e6f537d61433534ff7e82bb285a2d3e1b7a 100644 (file)
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -39,7 +39,7 @@
 #endif
 
 #define DBGP_DEFAULT 7
- 
+
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -123,7 +123,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
 
-#include "resourcemap.c" 
+#include "resourcemap.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
 
@@ -142,13 +142,13 @@ static void sio_setup(void)
         uint8_t byte;
 
         byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
-        byte |= 0x20; 
+        byte |= 0x20;
         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-        
+
         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
         dword |= (1<<0);
         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-        
+
         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
         dword |= (1<<16);
         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
@@ -165,7 +165,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                        (0xa<<3)|5, (0xa<<3)|7, 0, 0,
        };
 
-        struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE 
+        struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
                + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
         int needs_reset = 0;
@@ -209,7 +209,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         setup_mb_resource_map();
 
         uart_init();
-       
+
        /* Halt if there was a built in self test failure */
        report_bist_failure(bist);
 
@@ -281,7 +281,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         //It's the time to set ctrl in sysinfo now;
        fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 
-        enable_smbus(); 
+        enable_smbus();
 
         /* all ap stopped? */