remove trailing whitespace

[coreboot.git] / src / mainboard / getac / p470 / romstage.c

diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index ecc9e4bb03e6d29290a6cb72a57d2483fe5a05d3..afad4bc82093d83633051410c340f935395aaae8 100644 (file)
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2007-2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
@@ -19,10 +19,6 @@
  * MA 02110-1301 USA
  */
 
-/* Configuration of the i945 driver */
-#define CHIPSET_I945GM 1
-#define CHANNEL_XOR_RANDOMIZATION 1
-
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>
@@ -30,26 +26,16 @@
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
-
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-
+#include <lib.h>
+#include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
-
-#if CONFIG_USBDEBUG_DIRECT
-#define DBGP_DEFAULT 0
-#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
-#include "pc80/usbdebug_direct_serial.c"
-#endif
-
-#include "lib/ramtest.c"
-#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
-
-#include "northbridge/intel/i945/udelay.c"
-
+#include "northbridge/intel/i945/i945.h"
+#include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
-static void setup_ich7_gpios(void)
+#include "option_table.h"
+
+void setup_ich7_gpios(void)
 {
        u32 gpios;
 
@@ -93,26 +79,18 @@ static void setup_ich7_gpios(void)
        outl(gpios, DEFAULT_GPIOBASE + 0x0c);   /* GP_LVL */
 }
 
-#include "northbridge/intel/i945/early_init.c"
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-       return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/i945/raminit.h"
-#include "northbridge/intel/i945/raminit.c"
-#include "northbridge/intel/i945/errata.c"
-#include "northbridge/intel/i945/debug.c"
-
 static void ich7_enable_lpc(void)
 {
+       int lpt_en = 0;
+       if (read_option(lpt, 0) != 0) {
+              lpt_en = 1<<2; // enable LPT
+       }
        // Enable Serial IRQ
        pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
        // decode range
        pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007);
        // decode range
-       pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
+       pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en);
        // Enable 0x02e0 - 0x2ff
        pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x001c02e1);
        // Enable 0x600 - 0x6ff
@@ -121,7 +99,6 @@ static void ich7_enable_lpc(void)
        pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069);
 }
 
-
 /* This box has two superios, so enabling serial becomes slightly excessive.
  * We disable a lot of stuff to make sure that there are no conflicts between
  * the two. Also set up the GPIOs from the beginning. This is the "no schematic
@@ -289,41 +266,25 @@ static void early_ich7_init(void)
 
 #include <cbmem.h>
 
-// Now, this needs to be included because it relies on the symbol
-// __PRE_RAM_ being set during CAR stage (in order to compile the 
-// BSS free versions of the functions). Either rewrite the code
-// to be always BSS free, or invent a flag that's better suited than
-// __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
-//
-#include "lib/cbmem.c"
-
 void main(unsigned long bist)
 {
        u32 reg32;
        int boot_mode = 0;
 
-       if (bist == 0) {
+       if (bist == 0)
                enable_lapic();
-       }
 
 #if 0
        /* Force PCIRST# */
        pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
-       udelay(200);
+       udelay(200 * 1000);
        pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
-       udelay(200);
 #endif
 
        ich7_enable_lpc();
        early_superio_config();
 
        /* Set up the console */
-       uart_init();
-
-#if CONFIG_USBDEBUG_DIRECT
-       i82801gx_enable_usbdebug_direct(DBGP_DEFAULT);
-       early_usbdebug_direct_init();
-#endif
        console_init();
 
        /* Halt if there was a built in self test failure */
@@ -359,18 +320,18 @@ void main(unsigned long bist)
 
        /* Enable SPD ROMs and DDR-II DRAM */
        enable_smbus();
-       
+
 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
        dump_spd_registers();
 #endif
 
-       sdram_initialize(boot_mode);
+       sdram_initialize(boot_mode, NULL);
 
        /* Perform some initialization that must run before stage2 */
        early_ich7_init();
 
-       /* This should probably go away. Until now it is required 
-        * and mainboard specific 
+       /* This should probably go away. Until now it is required
+        * and mainboard specific
         */
        rcba_config();
 
@@ -382,7 +343,7 @@ void main(unsigned long bist)
 
 #if CONFIG_HAVE_ACPI_RESUME == 0
        /* When doing resume, we must not overwrite RAM */
-#if defined(DEBUG_RAM_SETUP)
+#if CONFIG_DEBUG_RAM_SETUP
        sdram_dump_mchbar_registers();
 
        {
@@ -412,12 +373,11 @@ void main(unsigned long bist)
                 * memory completely, but that's a wonderful clean up task for another
                 * day.
                 */
-               if (resume_backup_memory) 
+               if (resume_backup_memory)
                        memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
 
                /* Magic for S3 resume */
-               pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+               pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
        }
 #endif
 }
-