/*
* This file is part of the coreboot project.
- *
+ *
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <lib.h>
-#include <usbdebug.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
static void ich7_enable_lpc(void)
{
int lpt_en = 0;
- if (read_option(CMOS_VSTART_lpt, CMOS_VLEN_lpt, 0) != 0) {
+ if (read_option(lpt, 0) != 0) {
lpt_en = 1<<2; // enable LPT
}
// Enable Serial IRQ
early_superio_config();
/* Set up the console */
- uart_init();
-
console_init();
/* Halt if there was a built in self test failure */
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-
+
#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
dump_spd_registers();
#endif
/* Perform some initialization that must run before stage2 */
early_ich7_init();
- /* This should probably go away. Until now it is required
- * and mainboard specific
+ /* This should probably go away. Until now it is required
+ * and mainboard specific
*/
rcba_config();
* memory completely, but that's a wonderful clean up task for another
* day.
*/
- if (resume_backup_memory)
+ if (resume_backup_memory)
memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
/* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
}
#endif
}