m5a99x-evo: grml, strange romstage ld warning... dunno why :/

[coreboot.git] / src / mainboard / asus / m5a99x-evo / romstage.c

diff --git a/src/mainboard/asus/m5a99x-evo/romstage.c b/src/mainboard/asus/m5a99x-evo/romstage.c
index 9d8e08ac66164e3ca3ae58f1d4b37f2ee2a2b766..8091f8e59fffbf3f7f1dd7d87ce64bddf765b023 100644 (file)
--- a/src/mainboard/asus/m5a99x-evo/romstage.c
+++ b/src/mainboard/asus/m5a99x-evo/romstage.c
@@ -47,9 +47,9 @@
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 #include "southbridge/amd/rs780/early_setup.c"
-#include <sb_cimx.h>
-#include <SBPLATFORM.h> /* SB OEM constants */
-#include <southbridge/amd/cimx/sb800/smbus.h>
+#include <southbridge/amd/cimx/sb900/SbEarly.h>
+#include <southbridge/amd/cimx/sb900/SbPlatform.h> /* SB OEM constants */
+#include <southbridge/amd/cimx/sb900/smbus.h>
 #include "northbridge/amd/amdfam10/debug.c"
 
 static void activate_spd_rom(const struct mem_controller *ctrl)
@@ -98,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                enumerate_ht_chain();
 
                //enable port80 decoding and southbridge poweron init
-               sb_Poweron_Init();
+               sb_poweron_init();
        }
 
        post_code(0x30);
@@ -111,7 +111,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        post_code(0x32);
 
        enable_rs780_dev8();
-       sb800_clk_output_48Mhz();
+       // sb800_clk_output_48Mhz();
 
        it8721f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();