m5a99x-evo: raminit not ok? :-/

[coreboot.git] / src / mainboard / asus / m5a99x-evo / romstage.c

diff --git a/src/mainboard/asus/m5a99x-evo/romstage.c b/src/mainboard/asus/m5a99x-evo/romstage.c
index 9d8e08ac66164e3ca3ae58f1d4b37f2ee2a2b766..424c9a97c69371dbabefa6d6ef93b69816b00e45 100644 (file)
--- a/src/mainboard/asus/m5a99x-evo/romstage.c
+++ b/src/mainboard/asus/m5a99x-evo/romstage.c
@@ -46,10 +46,10 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/early_setup.c"
-#include <sb_cimx.h>
-#include <SBPLATFORM.h> /* SB OEM constants */
-#include <southbridge/amd/cimx/sb800/smbus.h>
+#include "nb_cimx.h"
+#include <southbridge/amd/cimx/sb900/SbEarly.h>
+#include <southbridge/amd/cimx/sb900/SbPlatform.h> /* SB OEM constants */
+#include <southbridge/amd/cimx/sb900/smbus.h>
 #include "northbridge/amd/amdfam10/debug.c"
 
 static void activate_spd_rom(const struct mem_controller *ctrl)
@@ -98,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                enumerate_ht_chain();
 
                //enable port80 decoding and southbridge poweron init
-               sb_Poweron_Init();
+               sb_poweron_init();
        }
 
        post_code(0x30);
@@ -110,14 +110,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        post_code(0x32);
 
-       enable_rs780_dev8();
-       sb800_clk_output_48Mhz();
-
        it8721f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
        console_init();
        printk(BIOS_DEBUG, "\n");
 
+
 //     dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 
        /* Halt if there was a built in self test failure */
@@ -169,8 +167,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        post_code(0x38);
 
-       /* run _early_setup before soft-reset. */
-       rs780_early_setup();
+       sr56x0_rd890_disable_pcie_bridge();
+       nb_Poweron_Init();
 
 #if CONFIG_SET_FIDVID == 1
        msr = rdmsr(0xc0010071);
@@ -190,7 +188,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 #endif
 
-       rs780_htinit();
+       nb_Ht_Init();
 
        /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
        if (!warm_reset_detect(0)) {
@@ -225,7 +223,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 //     die("After MCT init before CAR disabled.");
 
+#if 0
        rs780_before_pci_init();
+#endif
 
        post_code(0x42);
        post_cache_as_ram();    // BSP switch stack to ram, copy then execute LB.