uart_init();
console_init();
printk(BIOS_DEBUG, "\n");
- printk(BIOS_DEBUG, "zomg1\n");
- sr56x0_rd890_disable_pcie_bridge();
-
- printk(BIOS_DEBUG, "zomg2\n");
- nb_Poweron_Init();
- printk(BIOS_DEBUG, "zomg3\n");
- nb_Ht_Init();
- printk(BIOS_DEBUG, "zomg4\n");
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
post_code(0x38);
- /* run _early_setup before soft-reset. */
-#if 0
- rs780_early_setup();
-#endif
+ sr56x0_rd890_disable_pcie_bridge();
+ nb_Poweron_Init();
#if CONFIG_SET_FIDVID == 1
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
#endif
-#if 0
- rs780_htinit();
-#endif
+ nb_Ht_Init();
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {