/* DefinitionBlock Statement */
DefinitionBlock (
- "DSDT.AML", /* Output filename */
- "DSDT", /* Signature */
+ "DSDT.AML", /* Output filename */
+ "DSDT", /* Signature */
0x02, /* DSDT Revision, needs to be 2 for 64bit */
- "ASUS ", /* OEMID */
- "M5A99 ", /* TABLE ID */
+ "ASUS ", /* OEMID */
+ "M5A99 ", /* TABLE ID */
0x00010001 /* OEM Revision */
)
{ /* Start of ASL file */
- /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
+ /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */
/* Data to be patched by the BIOS during POST */
/* FIXME the patching is not done yet! */
) {
#include "acpi/cpstate.asl"
}
-
- Processor(
- CPU4, /* name space name */
- 4, /* Unique number for this processor */
- 0x0000, /* PBLK system I/O address !hardcoded! */
- 0x00 /* PBLKLEN for boot processor */
- ) {
- #include "acpi/cpstate.asl"
- }
-
- Processor(
- CPU5, /* name space name */
- 5, /* Unique number for this processor */
- 0x0000, /* PBLK system I/O address !hardcoded! */
- 0x00 /* PBLKLEN for boot processor */
- ) {
- #include "acpi/cpstate.asl"
- }
} /* End _PR scope */
- /* PIC IRQ mapping registers, C00h-C01h */
+ /* PIC IRQ mapping registers, C00h-C01h. */
OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
Field(PRQM, ByteAcc, NoLock, Preserve) {
PRQI, 0x00000008,
PRQD, 0x00000008, /* Offset: 1h */
}
IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
- PINA, 0x00000008, /* Index 0 */
- PINB, 0x00000008, /* Index 1 */
- PINC, 0x00000008, /* Index 2 */
- PIND, 0x00000008, /* Index 3 */
- AINT, 0x00000008, /* Index 4 */
- SINT, 0x00000008, /* Index 5 */
- , 0x00000008, /* Index 6 */
- AAUD, 0x00000008, /* Index 7 */
- AMOD, 0x00000008, /* Index 8 */
- PINE, 0x00000008, /* Index 9 */
- PINF, 0x00000008, /* Index A */
- PING, 0x00000008, /* Index B */
- PINH, 0x00000008, /* Index C */
+ PIRA, 0x00000008, /* Index 0 */
+ PIRB, 0x00000008, /* Index 1 */
+ PIRC, 0x00000008, /* Index 2 */
+ PIRD, 0x00000008, /* Index 3 */
+ PIRE, 0x00000008, /* Index 4 */
+ PIRF, 0x00000008, /* Index 5 */
+ PIRG, 0x00000008, /* Index 6 */
+ PIRH, 0x00000008, /* Index 7 */
}
/* PCI Error control register */
PM2D, 0x00000008,
}
- /* Power Management I/O registers */
+ /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
Field(PIOR, ByteAcc, NoLock, Preserve) {
PIOI, 0x00000008,
IO2S, 1,
IO1S, 1,
IO0S,1,
- Offset(0x20), /* AcpiPmEvtBlk */
+ Offset(0x20), /* AcpiPmEvtBlk. TODO: should be 0x60 */
APEB, 16,
Offset(0x36), /* GEvtLevelConfig */
, 6,
Store(Arg0, PMOD)
}
Method(CIRQ, 0x00, NotSerialized){
- Store(0, PINA)
- Store(0, PINB)
- Store(0, PINC)
- Store(0, PIND)
- Store(0, PINE)
- Store(0, PINF)
- Store(0, PING)
- Store(0, PINH)
+ Store(0, PIRA)
+ Store(0, PIRB)
+ Store(0, PIRC)
+ Store(0, PIRD)
+ Store(0, PIRE)
+ Store(0, PIRF)
+ Store(0, PIRG)
+ Store(0, PIRH)
}
Name(IRQB, ResourceTemplate(){
Name(_UID, 1)
Method(_STA, 0) {
- if (PINA) {
+ if (PIRA) {
Return(0x0B) /* sata is invisible */
} else {
Return(0x09) /* sata is disabled */
Method(_DIS ,0) {
/* DBGO("\\_SB\\LNKA\\_DIS\n") */
- Store(0, PINA)
+ Store(0, PIRA)
} /* End Method(_SB.INTA._DIS) */
Method(_PRS ,0) {
Method(_CRS ,0) {
/* DBGO("\\_SB\\LNKA\\_CRS\n") */
CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINA, IRQN)
+ ShiftLeft(1, PIRA, IRQN)
Return(IRQB)
} /* Method(_SB.INTA._CRS) */
if (Local0) {
Decrement(Local0)
}
- Store(Local0, PINA)
+ Store(Local0, PIRA)
} /* End Method(_SB.INTA._SRS) */
} /* End Device(INTA) */
Name(_UID, 2)
Method(_STA, 0) {
- if (PINB) {
+ if (PIRB) {
Return(0x0B) /* sata is invisible */
} else {
Return(0x09) /* sata is disabled */
Method(_DIS ,0) {
/* DBGO("\\_SB\\LNKB\\_DIS\n") */
- Store(0, PINB)
+ Store(0, PIRB)
} /* End Method(_SB.INTB._DIS) */
Method(_PRS ,0) {
Method(_CRS ,0) {
/* DBGO("\\_SB\\LNKB\\_CRS\n") */
CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINB, IRQN)
+ ShiftLeft(1, PIRB, IRQN)
Return(IRQB)
} /* Method(_SB.INTB._CRS) */
if (Local0) {
Decrement(Local0)
}
- Store(Local0, PINB)
+ Store(Local0, PIRB)
} /* End Method(_SB.INTB._SRS) */
} /* End Device(INTB) */
Name(_UID, 3)
Method(_STA, 0) {
- if (PINC) {
+ if (PIRC) {
Return(0x0B) /* sata is invisible */
} else {
Return(0x09) /* sata is disabled */
Method(_DIS ,0) {
/* DBGO("\\_SB\\LNKC\\_DIS\n") */
- Store(0, PINC)
+ Store(0, PIRC)
} /* End Method(_SB.INTC._DIS) */
Method(_PRS ,0) {
Method(_CRS ,0) {
/* DBGO("\\_SB\\LNKC\\_CRS\n") */
CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINC, IRQN)
+ ShiftLeft(1, PIRC, IRQN)
Return(IRQB)
} /* Method(_SB.INTC._CRS) */
if (Local0) {
Decrement(Local0)
}
- Store(Local0, PINC)
+ Store(Local0, PIRC)
} /* End Method(_SB.INTC._SRS) */
} /* End Device(INTC) */
Name(_UID, 4)
Method(_STA, 0) {
- if (PIND) {
+ if (PIRD) {
Return(0x0B) /* sata is invisible */
} else {
Return(0x09) /* sata is disabled */
Method(_DIS ,0) {
/* DBGO("\\_SB\\LNKD\\_DIS\n") */
- Store(0, PIND)
+ Store(0, PIRD)
} /* End Method(_SB.INTD._DIS) */
Method(_PRS ,0) {
Method(_CRS ,0) {
/* DBGO("\\_SB\\LNKD\\_CRS\n") */
CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PIND, IRQN)
+ ShiftLeft(1, PIRD, IRQN)
Return(IRQB)
} /* Method(_SB.INTD._CRS) */
if (Local0) {
Decrement(Local0)
}
- Store(Local0, PIND)
+ Store(Local0, PIRD)
} /* End Method(_SB.INTD._SRS) */
} /* End Device(INTD) */
Name(_UID, 5)
Method(_STA, 0) {
- if (PINE) {
+ if (PIRE) {
Return(0x0B) /* sata is invisible */
} else {
Return(0x09) /* sata is disabled */
Method(_DIS ,0) {
/* DBGO("\\_SB\\LNKE\\_DIS\n") */
- Store(0, PINE)
+ Store(0, PIRE)
} /* End Method(_SB.INTE._DIS) */
Method(_PRS ,0) {
Method(_CRS ,0) {
/* DBGO("\\_SB\\LNKE\\_CRS\n") */
CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINE, IRQN)
+ ShiftLeft(1, PIRE, IRQN)
Return(IRQB)
} /* Method(_SB.INTE._CRS) */
if (Local0) {
Decrement(Local0)
}
- Store(Local0, PINE)
+ Store(Local0, PIRE)
} /* End Method(_SB.INTE._SRS) */
} /* End Device(INTE) */
Name(_UID, 6)
Method(_STA, 0) {
- if (PINF) {
+ if (PIRF) {
Return(0x0B) /* sata is invisible */
} else {
Return(0x09) /* sata is disabled */
Method(_DIS ,0) {
/* DBGO("\\_SB\\LNKF\\_DIS\n") */
- Store(0, PINF)
+ Store(0, PIRF)
} /* End Method(_SB.INTF._DIS) */
Method(_PRS ,0) {
Method(_CRS ,0) {
/* DBGO("\\_SB\\LNKF\\_CRS\n") */
CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINF, IRQN)
+ ShiftLeft(1, PIRF, IRQN)
Return(IRQB)
} /* Method(_SB.INTF._CRS) */
if (Local0) {
Decrement(Local0)
}
- Store(Local0, PINF)
+ Store(Local0, PIRF)
} /* End Method(_SB.INTF._SRS) */
} /* End Device(INTF) */
Name(_UID, 7)
Method(_STA, 0) {
- if (PING) {
+ if (PIRG) {
Return(0x0B) /* sata is invisible */
} else {
Return(0x09) /* sata is disabled */
Method(_DIS ,0) {
/* DBGO("\\_SB\\LNKG\\_DIS\n") */
- Store(0, PING)
+ Store(0, PIRG)
} /* End Method(_SB.INTG._DIS) */
Method(_PRS ,0) {
Method(_CRS ,0) {
/* DBGO("\\_SB\\LNKG\\_CRS\n") */
CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PING, IRQN)
+ ShiftLeft(1, PIRG, IRQN)
Return(IRQB)
} /* Method(_SB.INTG._CRS) */
if (Local0) {
Decrement(Local0)
}
- Store(Local0, PING)
+ Store(Local0, PIRG)
} /* End Method(_SB.INTG._SRS) */
} /* End Device(INTG) */
Name(_UID, 8)
Method(_STA, 0) {
- if (PINH) {
+ if (PIRH) {
Return(0x0B) /* sata is invisible */
} else {
Return(0x09) /* sata is disabled */
Method(_DIS ,0) {
/* DBGO("\\_SB\\LNKH\\_DIS\n") */
- Store(0, PINH)
+ Store(0, PIRH)
} /* End Method(_SB.INTH._DIS) */
Method(_PRS ,0) {
Method(_CRS ,0) {
/* DBGO("\\_SB\\LNKH\\_CRS\n") */
CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINH, IRQN)
+ ShiftLeft(1, PIRH, IRQN)
Return(IRQB)
} /* Method(_SB.INTH._CRS) */
if (Local0) {
Decrement(Local0)
}
- Store(Local0, PINH)
+ Store(Local0, PIRH)
} /* End Method(_SB.INTH._SRS) */
} /* End Device(INTH) */
/* Clear wake status structure. */
Store(0, Index(WKST,0))
Store(0, Index(WKST,1))
- \_SB.PCI0.SIOS (Arg0)
} /* End Method(\_PTS) */
/*
* Store(Arg0, Index(WKST,1))
* }
*/
- \_SB.PCI0.SIOW (Arg0)
Return(WKST)
} /* End Method(\_WAK) */
/* Temp warning (TWarn) event */
Method(_L09) {
/* DBGO("\\_GPE\\_L09\n") */
- Notify (\_TZ.TZ00, 0x80)
+ /* Notify (\_TZ.TZ00, 0x80) */
}
/* Reserved */
Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
#include "acpi/usb.asl"
- /* System Bus */
+ /* South Bridge */
Scope(\_SB) { /* Start \_SB scope */
- #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
+ #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
/* _SB.PCI0 */
/* Note: Only need HID on Primary Bus */
Device(PCI0) {
External (TOM1)
- External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
+ External (TOM2)
Name(_HID, EISAID("PNP0A03"))
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
Method(_BBN, 0) { /* Bus number = 0 */
} /* end _PRT */
} /* end PBRa */
- Device(PBRb) {
- Name(_ADR, 0x000b0000)
+ Device(PE20) {
+ Name(_ADR, 0x00150000)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APSb) } /* APIC mode */
- Return (PSb) /* PIC Mode */
+ If(PMOD){ Return(APE0) } /* APIC mode */
+ Return (PE0) /* PIC Mode */
} /* end _PRT */
- } /* end PBRb */
-
- Device(PBRc) {
- Name(_ADR, 0x000c0000)
+ } /* end PE20 */
+ Device(PE21) {
+ Name(_ADR, 0x00150001)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APSc) } /* APIC mode */
- Return (PSc) /* PIC Mode */
+ If(PMOD){ Return(APE1) } /* APIC mode */
+ Return (PE1) /* PIC Mode */
} /* end _PRT */
- } /* end PBRc */
-
+ } /* end PE21 */
+ Device(PE22) {
+ Name(_ADR, 0x00150002)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APE2) } /* APIC mode */
+ Return (APE2) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PE22 */
+ Device(PE23) {
+ Name(_ADR, 0x00150003)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APE3) } /* APIC mode */
+ Return (PE3) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PE23 */
/* PCI slot 1, 2, 3 */
Device(PIBR) {
} /* end STCR */
Device(UOH1) {
- Name(_ADR, 0x00130000)
+ Name(_ADR, 0x00120000)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH1 */
Device(UOH2) {
- Name(_ADR, 0x00130001)
+ Name(_ADR, 0x00120002)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH2 */
Device(UOH3) {
- Name(_ADR, 0x00130002)
+ Name(_ADR, 0x00130000)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH3 */
Device(UOH4) {
- Name(_ADR, 0x00130003)
+ Name(_ADR, 0x00130002)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH4 */
Device(UOH5) {
- Name(_ADR, 0x00130004)
+ Name(_ADR, 0x00160000)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH5 */
+
+ Device(UOH6) {
+ Name(_ADR, 0x00160002)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH5 */
Device(UEH1) {
- Name(_ADR, 0x00130005)
+ Name(_ADR, 0x00140005)
Name(_PRW, Package() {0x0B, 3})
} /* end UEH1 */
/* Real Time Clock Device */
Device(RTC0) {
- Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
+ Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */
Name(_CRS, ResourceTemplate() {
IRQNoFlags(){8}
IO(Decode16,0x0070, 0x0070, 0, 2)
Name(_CRS, ResourceTemplate() {
DMA(Compatibility,BusMaster,Transfer8){4}
IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
- IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
- IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
- IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
- IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
+ IO(Decode16, 0x0081, 0x0081, 0x00, 0x03)
+ IO(Decode16, 0x0087, 0x0087, 0x00, 0x01)
+ IO(Decode16, 0x0089, 0x0089, 0x00, 0x03)
+ IO(Decode16, 0x008F, 0x008F, 0x00, 0x01)
IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
} /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
IRQNoFlags(){13}
})
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-
+#if 0
Device(HPTM) {
Name(_HID,EISAID("PNP0103"))
Name(CRS,ResourceTemplate() {
Return(CRS)
}
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+#endif
} /* end LIBR */
Device(HPBR) {
Name(_ADR, 0x00140006)
} /* end Ac97modem */
- /* ITE8718 Support */
- OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
- Field (IOID, ByteAcc, NoLock, Preserve)
- {
- SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
- }
-
- IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
- {
- Offset (0x07),
- LDN, 8, /* Logical Device Number */
- Offset (0x20),
- CID1, 8, /* Chip ID Byte 1, 0x87 */
- CID2, 8, /* Chip ID Byte 2, 0x12 */
- Offset (0x30),
- ACTR, 8, /* Function activate */
- Offset (0xF0),
- APC0, 8, /* APC/PME Event Enable Register */
- APC1, 8, /* APC/PME Status Register */
- APC2, 8, /* APC/PME Control Register 1 */
- APC3, 8, /* Environment Controller Special Configuration Register */
- APC4, 8 /* APC/PME Control Register 2 */
- }
-
- /* Enter the 8718 MB PnP Mode */
- Method (EPNP)
- {
- Store(0x87, SIOI)
- Store(0x01, SIOI)
- Store(0x55, SIOI)
- Store(0x55, SIOI) /* 8718 magic number */
- }
- /* Exit the 8718 MB PnP Mode */
- Method (XPNP)
- {
- Store (0x02, SIOI)
- Store (0x02, SIOD)
- }
- /*
- * Keyboard PME is routed to SB700 Gevent3. We can wake
- * up the system by pressing the key.
- */
- Method (SIOS, 1)
- {
- /* We only enable KBD PME for S5. */
- If (LLess (Arg0, 0x05))
- {
- EPNP()
- /* DBGO("8718F\n") */
-
- Store (0x4, LDN)
- Store (One, ACTR) /* Enable EC */
- /*
- Store (0x4, LDN)
- Store (0x04, APC4)
- */ /* falling edge. which mode? Not sure. */
-
- Store (0x4, LDN)
- Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
- Store (0x4, LDN)
- Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
-
- XPNP()
- }
- }
- Method (SIOW, 1)
- {
- EPNP()
- Store (0x4, LDN)
- Store (Zero, APC0) /* disable keyboard PME */
- Store (0x4, LDN)
- Store (0xFF, APC1) /* clear keyboard PME status */
- XPNP()
- }
-
Name(CRES, ResourceTemplate() {
IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
0x0000, /* translation */
0xF300 /* length */
)
-
#if 0
Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
0x00000000, /* Min */
0x00000000, /* Max */
0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
+ 0x00000000, /* Max-Min, RLEN */
,,
PCBM
)
/* DRAM memory from 4GB to TopMem2 */
QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, /* Granularity */
- 0x00000000, /* Min */
+ 0xFFFFFFFF, /* Granularity */
+ 0x00000000, /* Min */
0x00000000, /* Max */
0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
+ 0x00000000, /* Max-Min, RLEN */
,,
DMHI
)
/* BIOS space just below 16EB */
QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, /* Granularity */
+ 0xFFFFFFFF, /* Granularity */
0x00000000, /* Min */
- 0x00000000, /* Max */
+ 0x00000000, /* Max */
0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
+ 0x00000000, /* Max-Min, RLEN */
,,
PEBM
)
#endif
-
- /* memory space for PCI BARs below 4GB */
- Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
+ /* memory space for PCI BARs below 4GB */
+ Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
}) /* End Name(_SB.PCI0.CRES) */
Method(_CRS, 0) {
/* DBGO("\\_SB\\PCI0\\_CRS\n") */
-
#if 0
CreateDWordField(CRES, ^EMM1._BAS, EM1B)
CreateDWordField(CRES, ^EMM1._LEN, EM1L)
Store(PBLN,EBML)
}
#endif
-
- CreateDWordField(CRES, ^MMIO._BAS, MM1B)
- CreateDWordField(CRES, ^MMIO._LEN, MM1L)
- /*
- * Declare memory between TOM1 and 4GB as available
- * for PCI MMIO.
- * Use ShiftLeft to avoid 64bit constant (for XP).
- * This will work even if the OS does 32bit arithmetic, as
- * 32bit (0x00000000 - TOM1) will wrap and give the same
- * result as 64bit (0x100000000 - TOM1).
- */
- Store(TOM1, MM1B)
- ShiftLeft(0x10000000, 4, Local0)
- Subtract(Local0, TOM1, Local0)
- Store(Local0, MM1L)
+ CreateDWordField(CRES, ^MMIO._BAS, MM1B)
+ CreateDWordField(CRES, ^MMIO._LEN, MM1L)
+ /*
+ * Declare memory between TOM1 and 4GB as available
+ * for PCI MMIO.
+ * Use ShiftLeft to avoid 64bit constant (for XP).
+ * This will work even if the OS does 32bit arithmetic, as
+ * 32bit (0x00000000 - TOM1) will wrap and give the same
+ * result as 64bit (0x100000000 - TOM1).
+ */
+ Store(TOM1, MM1B)
+ ShiftLeft(0x10000000, 4, Local0)
+ Subtract(Local0, TOM1, Local0)
+ Store(Local0, MM1L)
Return(CRES) /* note to change the Name buffer */
} /* end of Method(_SB.PCI0._CRS) */
/* DBGO("\n") */
}
} /* End Scope SI */
-
+#if 0
/* SMBUS Support */
Mutex (SBX0, 0x00)
OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
} /* end of _TMP */
} /* end of TZ00 */
}
+#endif
}
/* End of ASL file */
projects / coreboot.git / blobdiff