Use DIMM0 et al in lots more places instead of hardocding values.

[coreboot.git] / src / mainboard / asus / a8n_e / romstage.c

diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c
index b9253aa4c4f9585432e99f6bef411b3f5f6f5791..155f414668272179382d5ead33a03ee3aee878ed 100644 (file)
--- a/src/mainboard/asus/a8n_e/romstage.c
+++ b/src/mainboard/asus/a8n_e/romstage.c
@@ -48,6 +48,7 @@
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "cpu/amd/dualcore/dualcore.c"
+#include <spd.h>
 
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
@@ -93,11 +94,11 @@ static void sio_setup(void)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
-               (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
-               (0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
+               DIMM0, DIMM2, 0, 0,
+               DIMM1, DIMM3, 0, 0,
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
-               (0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
-               (0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
+               DIMM4, DIMM6, 0, 0,
+               DIMM5, DIMM7, 0, 0,
 #endif
        };