remove trailing whitespace

[coreboot.git] / src / mainboard / amd / tilapia_fam10 / mainboard.c

diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c
index b2b0525503524942b49c7cebede7d1062a48344a..357bdac230ea8efc02a8aee0a6ccafd7c006a496 100644 (file)
--- a/src/mainboard/amd/tilapia_fam10/mainboard.c
+++ b/src/mainboard/amd/tilapia_fam10/mainboard.c
@@ -26,15 +26,12 @@
 #include <cpu/amd/mtrr.h>
 #include <device/pci_def.h>
 #include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/smbus.h"
 #include "chip.h"
 
 #define ADT7461_ADDRESS 0x4C
 #define ARA_ADDRESS     0x0C /* Alert Response Address */
 
-extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
-                              u8 val);
-
 #define ADT7461_read_byte(address) \
        do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
 #define ARA_read_byte(address) \
@@ -42,12 +39,11 @@ extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
 #define ADT7461_write_byte(address, val) \
        do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
 
-#define SMBUS_IO_BASE 0x6000
-
 uint64_t uma_memory_base, uma_memory_size;
 
 void set_pcie_dereset(void);
 void set_pcie_reset(void);
+u8 is_dev3_present(void);
 
 void set_pcie_dereset()
 {
@@ -129,6 +125,90 @@ static void get_ide_dma66(void)
 }
 #endif
 
+/*
+ * justify the dev3 is exist or not
+ */
+u8 is_dev3_present(void)
+{
+       u16 word;
+       device_t sm_dev;
+
+       /* access the smbus extended register */
+       sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+       /* put the GPIO68 output to tristate */
+       word = pci_read_config16(sm_dev, 0x7e);
+       word |= 1 << 6;
+       pci_write_config16(sm_dev, 0x7e,word);
+
+       /* read the GPIO68 input status */
+       word = pci_read_config16(sm_dev, 0x7e);
+
+       if(word & (1 << 10)){
+               /*not exist*/
+               return 0;
+       }else{
+               /*exist*/
+               return 1;
+       }
+}
+
+
+/*
+ * set gpio40 gfx
+ */
+static void set_gpio40_gfx(void)
+{
+       u8 byte;
+       u32 dword;
+       device_t sm_dev;
+       /* disable the GPIO40 as CLKREQ2# function */
+       byte = pm_ioread(0xd3);
+       byte &= ~(1 << 7);
+       pm_iowrite(0xd3, byte);
+
+       /* disable the GPIO40 as CLKREQ3# function */
+       byte = pm_ioread(0xd4);
+       byte &= ~(1 << 0);
+       pm_iowrite(0xd4, byte);
+
+       /* enable pull up for GPIO68 */
+       byte = pm2_ioread(0xf1);
+       byte &= ~(1 << 4);
+       pm2_iowrite(0xf1, byte);
+
+       /* access the smbus extended register */
+       sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+       /*if the dev3 is present, set the gfx to 2x8 lanes*/
+       /*otherwise set the gfx to 1x16 lanes*/
+       if(is_dev3_present()){
+
+               printk(BIOS_INFO, "Dev3 is present. GFX Configuration is Two x8 slots\n");
+               /* when the gpio40 is configured as GPIO, this will enable the output */
+               pci_write_config32(sm_dev, 0xf8, 0x4);
+               dword = pci_read_config32(sm_dev, 0xfc);
+               dword &= ~(1 << 10);
+
+               /* When the gpio40 is configured as GPIO, this will represent the output value*/
+               /* 1 :enable two x8  , 0 : master slot enable only */
+               dword |= (1 << 26);
+               pci_write_config32(sm_dev, 0xfc, dword);
+
+       }else{
+               printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
+               /* when the gpio40 is configured as GPIO, this will enable the output */
+               pci_write_config32(sm_dev, 0xf8, 0x4);
+               dword = pci_read_config32(sm_dev, 0xfc);
+               dword &= ~(1 << 10);
+
+               /* When the gpio40 is configured as GPIO, this will represent the output value*/
+               /* 1 :enable two x8  , 0 : master slot enable only */
+               dword &=  ~(1 << 26);
+               pci_write_config32(sm_dev, 0xfc, dword);
+       }
+}
+
 /*
  * set thermal config
  */
@@ -199,10 +279,6 @@ static void set_thermal_config(void)
 *************************************************/
 static void tilapia_enable(device_t dev)
 {
-       /* Leave it for furture use. */
-       /* struct mainboard_config *mainboard =
-          (struct mainboard_config *)dev->chip_info; */
-
        printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev);
 
 #if (CONFIG_GFXUMA == 1)
@@ -247,6 +323,7 @@ static void tilapia_enable(device_t dev)
        set_pcie_dereset();
        /* get_ide_dma66(); */
        set_thermal_config();
+       set_gpio40_gfx();
 }
 
 int add_mainboard_resources(struct lb_memory *mem)