- Moved hlt() to it's own header.

[coreboot.git] / src / mainboard / amd / solo / auto.c

diff --git a/src/mainboard/amd/solo/auto.c b/src/mainboard/amd/solo/auto.c
index 5963934fd510e71ee743b8bc55cd96320e1390d3..3a80e4c1bdd7087f0b9dca99dbfc4d16da0d5922 100644 (file)
--- a/src/mainboard/amd/solo/auto.c
+++ b/src/mainboard/amd/solo/auto.c
@@ -1,14 +1,16 @@
 #define ASSEMBLY 1
 #include <stdint.h>
 #include <device/pci_def.h>
-#include <cpu/p6/apic.h>
 #include <arch/io.h>
 #include <device/pnp.h>
 #include <arch/romcc_io.h>
+#include <arch/smp/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
-#include "northbridge/amd/amdk8/early_ht.c"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/k8/apic_timer.c"
@@ -17,9 +19,26 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "debug.c"
 #include "northbridge/amd/amdk8/cpu_rev.c"
+#include "superio/NSC/pc87360/pc87360_early_serial.c"
 
 #define SIO_BASE 0x2e
 
+static void hard_reset(void)
+{
+       set_bios_reset();
+
+       /* enable cf9 */
+       pci_write_config8(PCI_DEV(0, 0x05, 3), 0x41, 0xf1);
+       /* reset */
+       outb(0x0e, 0x0cf9);
+}
+
+static void soft_reset(void)
+{
+       set_bios_reset();
+       pci_write_config8(PCI_DEV(0, 0x05, 0), 0x47, 1);
+}
+
 static void memreset_setup(void)
 {
        if (is_cpu_pre_c0()) {
@@ -54,7 +73,7 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
 
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
-       /* nothing here */
+       /* nothing to do */
 }
 
 static inline int spd_read_byte(unsigned device, unsigned address)
@@ -62,69 +81,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
        return smbus_read_byte(device, address);
 }
 
-/* no specific code here. this should go away completely */
-static void coherent_ht_mainboard(unsigned cpus)
-{
-}
 
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "sdram/generic_sdram.c"
 
-static void enable_lapic(void)
-{
-
-       msr_t msr;
-       msr = rdmsr(0x1b);
-       msr.hi &= 0xffffff00;
-       msr.lo &= 0x000007ff;
-       msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
-       wrmsr(0x1b, msr);
-}
-
-static void stop_this_cpu(void)
-{
-       unsigned apicid;
-       apicid = apic_read(APIC_ID) >> 24;
-
-       /* Send an APIC INIT to myself */
-       apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
-       apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
-       /* Wait for the ipi send to finish */
-       apic_wait_icr_idle();
-
-       /* Deassert the APIC INIT */
-       apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
-       apic_write(APIC_ICR,  APIC_INT_LEVELTRIG | APIC_DM_INIT);
-       /* Wait for the ipi send to finish */
-       apic_wait_icr_idle();
-
-       /* If I haven't halted spin forever */
-       for(;;) {
-               hlt();
-       }
-}
-
-#define PC87360_FDC  0x00
-#define PC87360_PP   0x01
-#define PC87360_SP2  0x02
-#define PC87360_SP1  0x03
-#define PC87360_SWC  0x04
-#define PC87360_KBCM 0x05
-#define PC87360_KBCK 0x06
-#define PC87360_GPIO 0x07
-#define PC87360_ACB  0x08
-#define PC87360_FSCM 0x09
-#define PC87360_WDT  0x0A
-
-/* FIXME: Do we really need this on Solo boards? */
-static void pc87360_enable_serial(void)
-{
-       pnp_set_logical_device(SIO_BASE, PC87360_SP1);
-       pnp_set_enable(SIO_BASE, 1);
-       pnp_set_iobase0(SIO_BASE, 0x3f8);
-}
-
 static void main(void)
 {
        static const struct mem_controller cpu[] = {
@@ -138,26 +99,29 @@ static void main(void)
                        .channel1 = { 0, 0, 0, 0 },
                }
        };
+       int needs_reset;
+       enable_lapic();
+       init_timer();
        if (cpu_init_detected()) {
                asm("jmp __cpu_reset");
        }
        enable_lapic();
        init_timer();
-
-#if 0
-       /* Enabling this will make romcc segfault - 2003/10/13 */
+       distinguish_cpu_resets();
        if (!boot_cpu()) {
                print_err("This LinuxBIOS image is built for UP only.\n");
+               stop_this_cpu();
        }
-#endif
-       pc87360_enable_serial();
+       pc87360_enable_serial(SIO_BASE, TTYS0_BASE);
        uart_init();
        console_init();
        setup_default_resource_map();
-       setup_coherent_ht_domain();
-       enumerate_ht_chain(0);
-       distinguish_cpu_resets(0);
-       
+       needs_reset = setup_coherent_ht_domain();
+       needs_reset = ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
+       if (needs_reset) {
+               print_info("ht reset -");
+               soft_reset();
+       }
 #if 0
        print_pci_devices();
 #endif