Merge all spd_addr.h into the resp. romstage.c files.

[coreboot.git] / src / mainboard / amd / serengeti_cheetah_fam10 / romstage.c

diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index c6864b92c14ad4d56244ac2d3e18e72a7a149b5b..cb5c070f63ea8c01bb0dfa88c9fa00d2639e496f 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -39,6 +39,7 @@
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include <lib.h>
+#include <spd.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
@@ -105,7 +106,98 @@ static int spd_read_byte(u32 device, u32 address)
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
-#include "spd_addr.h"
+static const u8 spd_addr[] = {
+       //first node
+       RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+       //second node
+       RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
+#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 2
+       // third node
+       RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       // forth node
+       RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
+#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 4
+       RC04, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC05, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 6
+       RC06, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC07, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 8
+       RC08, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC09, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC10, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC11, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 12
+       RC12, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC13, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC14, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC15, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 16
+       RC16, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC17, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC18, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC19, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 20
+       RC20, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC21, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC22, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC23, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 24
+       RC24, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC25, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC26, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC27, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC28, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC29, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC30, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC31, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 32
+       RC32, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC33, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC34, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC35, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC36, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC37, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC38, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC39, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC40, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC41, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC42, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC43, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC44, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC45, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC46, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC47, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 48
+       RC48, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC49, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC50, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC51, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC52, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC53, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC54, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC55, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC56, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC57, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC58, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC59, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC60, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC61, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC62, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+       RC63, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#endif
+};
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {