Since some people disapprove of white space cleanups mixed in regular commits

[coreboot.git] / src / mainboard / amd / serengeti_cheetah / resourcemap.c

diff --git a/src/mainboard/amd/serengeti_cheetah/resourcemap.c b/src/mainboard/amd/serengeti_cheetah/resourcemap.c
index 9b19503360c9d02c6849ce8975c9b595a565b11a..be11b689da84724a5af6f6cc9e2c7de2bddeaabb 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah/resourcemap.c
+++ b/src/mainboard/amd/serengeti_cheetah/resourcemap.c
@@ -143,7 +143,7 @@ static void setup_mb_resource_map(void)
                 *         1 = base/limit registers i are read-only
                 * [ 7: 4] Reserved
                 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
-                *         This field defines the upper address bits of a 40bit address 
+                *         This field defines the upper address bits of a 40bit address
                 *         that defines the start of memory-mapped I/O region i
                 */
                PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
@@ -199,7 +199,7 @@ static void setup_mb_resource_map(void)
                 * [ 3: 2] Reserved
                 * [ 4: 4] VGA Enable
                 *         0 = VGA matches Disabled
-                *         1 = matches all address < 64K and where A[9:0] is in the 
+                *         1 = matches all address < 64K and where A[9:0] is in the
                 *             range 3B0-3BB or 3C0-3DF independen of the base & limit registers
                 * [ 5: 5] ISA Enable
                 *         0 = ISA matches Disabled
@@ -207,7 +207,7 @@ static void setup_mb_resource_map(void)
                 *             from matching agains this base/limit pair
                 * [11: 6] Reserved
                 * [24:12] PCI I/O Base i
-                *         This field defines the start of PCI I/O region n 
+                *         This field defines the start of PCI I/O region n
                 * [31:25] Reserved
                 */
                PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,