* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
-
+
#include <stdint.h>
#include <string.h>
#include "agesawrapper.h"
#include "amdlib.h"
#include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
+#include <arch/io.h>
#define FILECODE UNASSIGNED_FILE_FILECODE
*----------------------------------------------------------------------------------------
*/
+#define MMCONF_ENABLE 1
+
/* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL;
VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL;
-VOID *AcpiAlib = NULL;
-
+VOID *AcpiAlib = NULL;
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
-
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
-
+
/*---------------------------------------------------------------------------------------
* L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------
*/
-UINT32
+UINT32
agesawrapper_amdinitcpuio (
VOID
)
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
-
+
/* Enable legacy video routing: D18F1xF4 VGA Enable */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
PciData = 1;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
PciData |= 1 << 7; // set NP (non-posted) bit
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
/* Map the remaining PCI hole as posted MMIO */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; // last address before non-posted range
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
/* Send all IO (0000-FFFF) to southbridge. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
PciData = 0x0000F000;
Status = AGESA_SUCCESS;
return (UINT32)Status;
}
-
-UINT32
+
+UINT32
agesawrapper_amdinitmmio (
VOID
)
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
-
+
+ UINT8 BusRangeVal = 0;
+ UINT8 BusNum;
+ UINT8 Index;
+
/*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register.
*/
- MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1;
+
+ for (Index = 0; Index < 8; Index++) {
+ BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
+ if (BusNum == 1) {
+ BusRangeVal = Index;
+ break;
+ }
+ }
+
+ MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE);
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
-
+
/*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
- MsrReg = MsrReg | 0x0000400000000000;
+ MsrReg = MsrReg | 0x0000400000000000ull;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
-
+
/* Set Ontario Link Data */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
PciData = 0x01308002;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-
- /* Set ROM cache onto WP to decrease post time */
- MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
- LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
- MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
- LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS;
return (UINT32)Status;
}
-UINT32
+UINT32
agesawrapper_amdinitreset (
VOID
)
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams;
-
+
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
-
LibAmdMemFill (&AmdResetParams,
0,
sizeof (AMD_RESET_PARAMS),
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0;
-
+
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct);
return (UINT32)status;
- }
-
-UINT32
+ }
+
+UINT32
agesawrapper_amdinitearly (
VOID
)
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
-
+
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
-
+
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly (AmdEarlyParamsPtr);
-
+
status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct);
return (UINT32)status;
}
-UINT32
+UINT32
agesawrapper_amdinitpost (
VOID
)
status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct);
+
/* Initialize heap space */
BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
return (UINT32)status;
}
-UINT32
+UINT32
agesawrapper_amdinitenv (
VOID
)
/* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18
- */
+ */
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
/* Initialize MMIO Base and Limit Address
* Modify B0D1F0x20
*/
}
}
-UINT32
+UINT32
agesawrapper_amdinitmid (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
-
+
/* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio ();
-
+
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
return (UINT32)status;
}
-UINT32
+UINT32
agesawrapper_amdinitlate (
VOID
)
ASSERT(Status == AGESA_SUCCESS);
}
- DmiTable = AmdLateParams.DmiTable;
- AcpiPstate = AmdLateParams.AcpiPState;
- AcpiSrat = AmdLateParams.AcpiSrat;
- AcpiSlit = AmdLateParams.AcpiSlit;
+ DmiTable = AmdLateParams.DmiTable;
+ AcpiPstate = AmdLateParams.AcpiPState;
+ AcpiSrat = AmdLateParams.AcpiSrat;
+ AcpiSlit = AmdLateParams.AcpiSlit;
- AcpiWheaMce = AmdLateParams.AcpiWheaMce;
- AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
- AcpiAlib = AmdLateParams.AcpiAlib;
+ AcpiWheaMce = AmdLateParams.AcpiWheaMce;
+ AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
+ AcpiAlib = AmdLateParams.AcpiAlib;
return (UINT32)Status;
}
-UINT32
+UINT32
agesawrapper_amdlaterunaptask (
- UINT32 Data,
+ UINT32 Func,
+ UINT32 Data,
VOID *ConfigPtr
)
{
AGESA_STATUS Status;
- AMD_LATE_PARAMS AmdLateParams;
+ AP_EXE_PARAMS ApExeParams;
- LibAmdMemFill (&AmdLateParams,
+ LibAmdMemFill (&ApExeParams,
0,
- sizeof (AMD_LATE_PARAMS),
- &(AmdLateParams.StdHeader));
-
- AmdLateParams.StdHeader.AltImageBasePtr = 0;
- AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
- AmdLateParams.StdHeader.Func = 0;
- AmdLateParams.StdHeader.ImageBasePtr = 0;
-
- Status = AmdLateRunApTask (&AmdLateParams);
+ sizeof (AP_EXE_PARAMS),
+ &(ApExeParams.StdHeader));
+
+ ApExeParams.StdHeader.AltImageBasePtr = 0;
+ ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ ApExeParams.StdHeader.Func = 0;
+ ApExeParams.StdHeader.ImageBasePtr = 0;
+ ApExeParams.StdHeader.ImageBasePtr = 0;
+ ApExeParams.FunctionNumber = Func;
+ ApExeParams.RelatedDataBlock = ConfigPtr;
+
+ Status = AmdLateRunApTask (&ApExeParams);
if (Status != AGESA_SUCCESS) {
agesawrapper_amdreadeventlog();
ASSERT(Status == AGESA_SUCCESS);
}
- DmiTable = AmdLateParams.DmiTable;
- AcpiPstate = AmdLateParams.AcpiPState;
- AcpiSrat = AmdLateParams.AcpiSrat;
- AcpiSlit = AmdLateParams.AcpiSlit;
-
- AcpiWheaMce = AmdLateParams.AcpiWheaMce;
- AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
- AcpiAlib = AmdLateParams.AcpiAlib;
-
return (UINT32)Status;
}
-UINT32
+UINT32
agesawrapper_amdreadeventlog (
VOID
)
AmdEventParams.StdHeader.ImageBasePtr = 0;
Status = AmdReadEventLog (&AmdEventParams);
while (AmdEventParams.EventClass != 0) {
- printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
- printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
- printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
+ printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
+ printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
+ printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
Status = AmdReadEventLog (&AmdEventParams);
}